公开(公告)号：US06423479B1

公开(公告)日：2002-07-23

申请号：US09495165

申请日：2000-01-31

Applicant: Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Bryan K. Choo

Inventor： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC: G03F726

CPC classification number: G03F1/82

Abstract: In one embodiment, the present invention relates to a method of processing a lithography mask, involving the steps of exposing a lithography substrate with actinic radiation through the lithography mask in a chamber; removing the lithography mask from the chamber, wherein the lithography mask contains carbon contaminants; and contacting the lithography mask with sulfur trioxide thereby reducing the carbon contaminants thereon.

Abstract translation: 在一个实施例中，本发明涉及一种处理光刻掩模的方法，包括以下步骤：将具有光化辐射的光刻基底通过室中的光刻掩模曝光; 从所述腔室去除所述光刻掩模，其中所述光刻掩模含有碳污染物; 并使光刻掩模与三氧化硫接触，从而减少其上的碳污染物。

公开(公告)号：US06417084B1

公开(公告)日：2002-07-09

申请号：US09620300

申请日：2000-07-20

Applicant: Bhanwar Singh ,  Marina Plat ,  Ramkumar Subramanian ,  Christopher F. Lyons

Inventor： Bhanwar Singh ,  Marina Plat ,  Ramkumar Subramanian ,  Christopher F. Lyons

IPC: H01L213205

CPC classification number: H01L21/28114 ,  H01L21/32139

Abstract: A method is provided for fabricating a T-gate structure. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer, and an ARC layer over the polysilicon layer. A gate structure is formed by removing the ARC layer and a portion of the polysilicon layer around a gate region. Spacers are then formed around the gate structure. Undercut regions are formed in the gate structure by performing an isotropic etch to provide the gate structure with a base region and a contact region. The base region has a width smaller than the contact region.

Abstract translation: 提供了一种用于制造T型栅结构的方法。 提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层以及多晶硅层上的ARC层。 通过在栅极区域周围除去ARC层和多晶硅层的一部分来形成栅极结构。 然后在栅极结构周围形成间隔物。 通过执行各向同性蚀刻在栅极结构中形成底切区域，以向栅极结构提供基极区域和接触区域。 基部区域的宽度小于接触区域。

公开(公告)号：US06391766B1

公开(公告)日：2002-05-21

申请号：US09788641

申请日：2001-02-21

Applicant: Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

Inventor： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC: H01L214763

CPC classification number: H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

Abstract: A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An inorganic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

Abstract translation: 一种形成互连结构的方法，其中有机低k介电材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 无机低k介电材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US06380067B1

公开(公告)日：2002-04-30

申请号：US09588119

申请日：2000-05-31

Applicant: Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

Inventor： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

IPC: H01L21302

CPC classification number: H01L21/76895 ,  H01L21/0276 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

Abstract: The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

Abstract translation: 本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。 在一个实施例中，电子器件形成在半导体衬底上。 然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。 然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。 然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。 然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。 光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

公开(公告)号：US06371134B1

公开(公告)日：2002-04-16

申请号：US09495014

申请日：2000-01-31

Applicant: Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Bryan K. Choo

Inventor： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC: B08B700

Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.

公开(公告)号：US06358856B1

公开(公告)日：2002-03-19

申请号：US09716215

申请日：2000-11-21

Applicant: Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

Inventor： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

IPC: H01L21311

CPC classification number: H01L21/31144

Abstract: A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.

Abstract translation: 形成小接触孔的方法使用亮场掩模在正抗蚀剂层中形成小圆筒。 在小圆筒周围形成负的抗蚀剂层，然后被蚀刻或抛光回去，使得暴露在负性抗蚀剂层上方的小圆筒的顶部部分留下。 负抗蚀剂层和小圆筒（正性抗蚀剂）暴露于光下，然后经受显影剂。 剩下的是一个位于小圆柱之前所在的小接触孔。

公开(公告)号：US06319802B1

公开(公告)日：2001-11-20

申请号：US09620145

申请日：2000-07-20

Applicant: Ramkumar Subramanian ,  Christopher F. Lyons ,  Bhanwar Singh ,  Marina Plat

Inventor： Ramkumar Subramanian ,  Christopher F. Lyons ,  Bhanwar Singh ,  Marina Plat

IPC: H01L213205

CPC classification number: H01L21/28114

Abstract: A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a sacrificial layer over the protection layer. An opening is then formed in the sacrificial layer. A contact material is deposited over the sacrificial layer filling the opening with the contact material and forming a contact layer. Portions of the contact material outside a gate region are then removed. Finally, the sacrificial layer and portions of the protection layer and the gate oxide layer not forming a part of the T-gate structure are removed.

Abstract translation: 提供了一种制造T型栅结构的方法。 提供了一种具有硅层的结构，该硅层具有栅极氧化物层，栅极氧化物层上的保护层和保护层上的牺牲层。 然后在牺牲层中形成开口。 接触材料沉积在用接触材料填充开口的牺牲层上并形成接触层。 然后去除栅极区域外部的接触材料的部分。 最后，除去牺牲层和不形成T栅结构的一部分的保护层和栅极氧化物层的部分。

公开(公告)号：US06294460B1

公开(公告)日：2001-09-25

申请号：US09586254

申请日：2000-05-31

Applicant: Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

Inventor： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota

IPC: H01L214763

CPC classification number: H01L21/7688 ,  H01L21/76802 ,  Y10S438/952

Abstract: A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, and a BARC is deposited on top of the dielectric layer. The BARC is deposited by PECVD to enrich the BARC with semiconductor material to increase the extinction coefficient of the BARC so its thickness can be reduced. A photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, developed, and removed. The BARC is then etched away in the pattern developed on the photoresist and the photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer. A conductive material is deposited over the BARC and the dielectric layer and is subsequently removed in the process of polishing the conductive material without requiring a separate BARC removal step.

Abstract translation: 提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。 在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，并且BARC沉积在电介质层的顶部上。 BARC通过PECVD沉积，以使BARC富集半导体材料，以增加BARC的消光系数，从而减小其厚度。 然后将厚度小于BARC的厚度的光致抗蚀剂层沉积在BARC的顶部。 然后将光致抗蚀剂图案化，光刻加工，显影和除去。 然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。 然后将BARC用作蚀刻电介质层的掩模。 导电材料沉积在BARC和电介质层上，随后在抛光导电材料的过程中被去除，而不需要单独的BARC去除步骤。

公开(公告)号：US06274289B1

公开(公告)日：2001-08-14

申请号：US09708104

申请日：2000-11-06

Applicant: Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

Inventor： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

IPC: G03F711

CPC classification number: G03F7/168 ,  G03F7/40

Abstract: In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.

Abstract translation: 在一个实施方案中，本发明涉及一种处理抗蚀剂层的方法，包括以下步骤：提供具有第一厚度的抗蚀剂层，抗蚀剂层包含具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与抗蚀剂层接触，以在抗蚀剂层和涂层之间的界面处形成去保护的抗蚀剂层; 以及去除涂层和去保护的抗蚀剂层，留下具有第二厚度的抗蚀剂，其中第二厚度小于第一厚度。

公开(公告)号：US20140060571A1

公开(公告)日：2014-03-06

申请号：US13831613

申请日：2013-03-15

Applicant: Glenn Mitchell ,  Ramkumar Subramanian ,  Carrie L. Wyse ,  Robert Torres, JR.

Inventor： Glenn Mitchell ,  Ramkumar Subramanian ,  Carrie L. Wyse ,  Robert Torres, JR.

IPC: B01J19/08 ,  B08B7/00 ,  B01J19/12

CPC classification number: B01J19/087 ,  B01J19/081 ,  B01J19/088 ,  B01J19/123 ,  B01J19/125 ,  B01J19/126 ,  B01J19/127 ,  B01J19/128 ,  B01J19/129 ,  B01J2219/0883 ,  B01J2219/0892 ,  C01B31/00 ,  C01B32/00 ,  C01B32/80 ,  C23C16/4405 ,  H01L21/31116 ,  Y02C20/30 ,  Y02P70/605

Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber. The additive(s) may be introduced upstream or downstream of the remote plasma such that both NF3 and the additive(s) (and any plasma-generated effluents) are present in the CVD chamber during cleaning.

Abstract translation: 根据本发明，提供分子蚀刻剂碳酰氟（COF 2）或其任何变体，以提高蚀刻和/或清洁和/或去除诸如不需要的膜和/或沉积物之类的材料的效率 处理室或基板（这里统称为“材料”）中的室壁和其它部件。 本发明的方法包括通过逐步添加添加剂，例如但不限于饱和的，不饱和的或部分不饱和的全氟化碳化合物（PFC）来点燃和维持等离子体，无论是远距离还是原位等离子体，其具有 通式（CyFz）和/或碳（COx）与三氟化氮（NF3）等离子体的氧化物进入化学沉积室（CVD）室，从而产生COF 2。 NF 3可以在CVD室内的等离子体中或在CVD室上游的远程等离子体区域中被激发。 添加剂可以被引入远程等离子体的上游或下游，使得NF 3和添加剂（和任何等离子体产生的流出物）在清洁期间都存在于CVD室中。