公开(公告)号：EP2863431B1

公开(公告)日：2017-04-26

申请号：EP15150443.8

申请日：2003-07-24

Applicant: Socionext Inc.

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/58 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 该半导体器件包括：在衬底10上形成的绝缘膜40,42; 埋入绝缘膜40,42的至少一个表面侧的配线58; 绝缘膜60,62，形成在绝缘膜42上，并包括具有弯曲成直角图案的孔状通孔60和槽状通孔66a; 以及掩埋在孔状通孔60和槽状通孔66a中的掩埋导体70,72a，其中槽状通孔66a形成为具有小于孔的宽度的宽度 从而防止埋入导体的填充不良，并且可以防止层间绝缘膜的破裂。 可以减少导体插头上的台阶，使得台阶不会影响上互连层和绝缘层。 因此，可以防止与上互连层的接触不良以及形成膜时发生的问题，并且因此半导体器件可以具有高水阻和高互连可靠性。

公开(公告)号：EP3059732A4

公开(公告)日：2017-04-19

申请号：EP14853892

申请日：2014-08-20

Applicant: SOCIONEXT INC

Inventor： MIYASAKA SHUJI ,  ABE KAZUTAKA ,  LIU ZONG XIAN ,  SIM YONG HWEE ,  TRAN ANH TUAN

IPC: G10L19/008 ,  G10L19/002 ,  H04S3/00 ,  H04S5/00 ,  H04S5/02

CPC classification number: G10L19/008 ,  G10L19/002 ,  H04S3/008 ,  H04S5/005 ,  H04S2400/11 ,  H04S2400/15

Abstract: An input signal includes a channel-based audio signal and an object-based audio signal, and an audio encoding device includes an audio scene analysis unit (100) configured to determine an audio scene from the input signal and detect audio scene information; a channel-based encoder (101) that encodes the channel-based audio signal output from the audio scene analysis unit; an object-based encoder (102) that encodes the object-based audio signal output from the audio scene analysis unit; and an audio scene encoding unit (103) configured to encode the audio scene information.

Abstract translation: 输入信号包括基于频道的音频信号和基于对象的音频信号，音频编码装置包括音频场景分析单元，配置为根据输入信号确定音频场景并检测音频场景信息; 基于频道的编码器（101），其对从音频场景分析单元输出的基于频道的音频信号进行编码; 基于对象的编码器（102），其对从音频场景分析单元输出的基于对象的音频信号进行编码; 和音频场景编码单元（103），被配置为对音频场景信息进行编码。

公开(公告)号：EP3136667A1

公开(公告)日：2017-03-01

申请号：EP15782326.1

申请日：2015-03-04

Applicant: Fujitsu Limited ,  Socionext Inc.

Inventor： LIU, Bo ,  YAN, Weizhen ,  LI, Lei ,  CHEN, Hao ,  RADECKI, Andrzej

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L5/006 ,  H04L25/03 ,  H04L27/265 ,  H04L2025/03636

Abstract: An adaptive equalizer, an adaptive equalization method and receiver. The adaptive equalizer is used for performing adaptive equalization processing on a frequency-domain signal, a channel used by the frequency-domain signal containing multiple subcarriers, the adaptive equalizer comprises: an equalizer coefficient generating unit configured to, for each subcarrier, generate an equalizer coefficient to which the subcarrier corresponds according to channel information and a step length of the subcarrier; wherein, different subcarriers correspond to different step lengths; and an equalization processing unit configured to, for each subcarrier, perform equalization processing on a signal in the subcarrier by using the equalizer coefficient.

Abstract translation: 自适应均衡器，自适应均衡方法和接收机。 自适应均衡器用于对频域信号进行自适应均衡处理，由包含多个子载波的频域信号使用的信道，所述自适应均衡器包括：均衡器系数生成单元，被配置为针对每个子载波生成均衡器 子载波对应的系数根据信道信息和子载波的步长; 其中，不同的子载波对应于不同的步长; 以及均衡处理单元，被配置为对于每个子载波，通过使用所述均衡器系数对所述子载波中的信号执行均衡处理。

公开(公告)号：EP2302921B1

公开(公告)日：2016-05-04

申请号：EP09797683.1

申请日：2009-07-13

Applicant: Socionext Inc.

Inventor： YANASE, Kazuhide ,  MATSUI, Takayuki ,  MORIYAMA, Eiichi ,  NAKAHIRA, Masahiro ,  KUBO, Yoko

IPC: H04N5/765 ,  G11B33/10 ,  H04N5/85 ,  H04N5/93 ,  H04N7/173

CPC classification number: H04N5/85 ,  H04N5/765 ,  H04N5/775 ,  H04N5/91 ,  H04N9/7921 ,  H04N9/8205 ,  H04N21/4122 ,  H04N21/4135 ,  H04N21/43622 ,  H04N21/43632

Abstract: The DVD player (10) includes: a reproducing unit (11) reproducing audio data and video data; a first transmission unit (12) converting, into first data in accordance with a first standard, the audio data and video data reproduced by the reproducing unit, and transmitting the first data to the television (100); a second transmission unit (13) converting, into second data in accordance with a second standard, the audio data and video data reproduced by the reproducing unit, and transmitting the second data to the television (100); a display determination unit (16) determining whether or not to display an error message regarding an error occurring in the first transmission unit (12) based on whether or not the video is displayed using the first data; and a display control unit (17) causing the message display unit to display the error message according to a result of the determination by the display determination unit.

公开(公告)号：EP2980842A1

公开(公告)日：2016-02-03

申请号：EP15178991.4

申请日：2015-07-30

Applicant: Socionext Inc.

Inventor： Urago, Kazuyuki ,  Shimizu, Nobutaka

IPC: H01L23/04 ,  H01L23/552

CPC classification number: H01L23/053 ,  H01L21/52 ,  H01L23/04 ,  H01L23/10 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1659 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively.

Abstract translation: 半导体器件包括：衬底; 设置在所述基板上的半导体元件; 多个电极，彼此分离设置在基板上，并且以平面图包围半导体元件; 覆盖所述半导体元件的盖，所述盖在平面图中包括内部部分和外部部分，所述外部部分在所述内部部分的外侧，所述盖子包括彼此分开设置的多个第一突出部件，所述第一突出部 构件设置在内部; 以及设置在所述多个电极之间的导电构件和分别设置在与所述多个电极相对的位置的所述多个突出构件，所述导电构件分别与所述多个电极和所述多个突出构件接合。

公开(公告)号：EP1369997B1

公开(公告)日：2016-01-20

申请号：EP03003649.5

申请日：2003-02-18

Applicant: Socionext Inc.

Inventor： Tanishima, Hideaki

IPC: H03K19/003 ,  G11C5/14 ,  G11C11/4074 ,  G05F1/46 ,  G05F3/24 ,  G06F13/40

CPC classification number: H03K19/00315

公开(公告)号：EP2866258A3

公开(公告)日：2015-07-29

申请号：EP14193115.4

申请日：2003-05-23

Applicant: Socionext Inc.

Inventor： Fujisawa, Tetsuya ,  Matsuki, Hirohisa ,  Igawa, Osamu ,  Aiba, Yoshitaka ,  Ikumo, Masamitsu ,  Sato, Mitsutaka

IPC: H01L23/538 ,  H01L21/60 ,  H01L23/544

CPC classification number: H01L24/29 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05599 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/24265 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A plurality of semiconductor devices formed on a silicon wafer which acts as a substrate of each semiconductor device, each semiconductor device comprising: a plurality of semiconductor elements (12,13) mounted on the substrate (11,31) via an adhesive layer (15) in a two-dimensional arrangement; a discrete resin layer (14) formed on said substrate and located around the associated semiconductor elements, the resin layer having substantially the same thickness as a thickness of the semiconductor elements; a discrete organic insulating layer (16) formed over a surface of the associated resin layer and circuit formation surfaces of the semiconductor elements so that edges of the organic insulating layer are located inward of the edges of the associated resin layer; a discrete rearrangement wiring layer (17) formed on the associated organic insulating layer and electrodes of said semiconductor chips so that edges of the rearrangement wiring layer are located inward of the edges of the associated organic insulating layer; and external connection terminals (18) electrically connected to the circuit formation surfaces of said semiconductor elements through wiring in the rearrangement wiring layer.

Abstract translation: 多个半导体器件形成在充当每个半导体器件的衬底的硅晶片上，每个半导体器件包括：多个半导体元件（12,13），经由粘合层（15）安装在衬底（11,31）上， ）以二维排列; 形成在所述衬底上并位于相关半导体元件周围的分立树脂层（14），所述树脂层具有与所述半导体元件的厚度基本相同的厚度; 形成在相关联的树脂层的表面和半导体元件的电路形成表面上的离散的有机绝缘层（16），使得有机绝缘层的边缘位于相关树脂层的边缘的内侧; 在相关有机绝缘层和所述半导体芯片的电极上形成的离散重排布线层（17），使得重排布线层的边缘位于相关有机绝缘层边缘的内侧; 和通过重排布线层中的布线电连接到所述半导体元件的电路形成表面的外部连接端子（18）。

公开(公告)号：EP4492778A1

公开(公告)日：2025-01-15

申请号：EP22930791.3

申请日：2022-03-09

Applicant: Socionext Inc.

Inventor： YAMAGISHI, Nobutaka ,  MAIER, Martin

IPC: H04N17/04

Abstract: To achieve inspection of warping processing at a low cost. A display control device includes an insertion unit configured to insert a determination image into a static region of time-series images, the static region being a region in which a pixel value does not change over time, a processing unit configured to execute warping processing on an image into which the determination image is inserted, and a determination unit configured to determine whether or not a result of a CRC computation performed on the static region of the image after the warping processing matches first reference information.

公开(公告)号：EP4485437A1

公开(公告)日：2025-01-01

申请号：EP22928506.9

申请日：2022-02-22

Applicant: Socionext Inc.

Inventor： TOMIOKA, Shinichi ,  YAMAGISHI, Nobutaka

IPC: G09G3/20 ,  G09G3/34 ,  G09G3/36

Abstract: An image display control device with a local dimming function includes: a brightness control unit to control brightness of a plurality of light sources based on first image information representing images to be displayed on a display unit, the light sources being included in a backlight; a pixel compensation unit to generate second image information by correcting pixel values included in the first image information based on the brightness of each light source; a first statistics obtaining unit to obtain first statistical data with respect to the pixel values included in the first image information; a second statistics obtaining unit to obtain second statistical data with respect to pixel values included in the second image information; and an anomaly detection unit to detect an anomaly of the brightness control unit or the pixel compensation unit based on the difference of the second statistical data from the first statistical data.

公开(公告)号：EP4258543A2

公开(公告)日：2023-10-11

申请号：EP23187969.3

申请日：2019-11-29

Applicant: Socionext Inc.

Inventor： MIKHAEL, David Hany Gaied ,  GERMANN, Bernd Hans

IPC: H03B27/00

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.