公开(公告)号：US20030214321A1

公开(公告)日：2003-11-20

申请号：US10407802

申请日：2003-04-04

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract translation: 一种改进的可编程逻辑设备架构，其通过在设备中的任何其他PLB上访问任何可编程逻辑块（PLB）的域中的定义的电路元件来提供资源的更有效的利用，通过在路由结构中并入选择性地连接 将PLB域中的电路元件的输入或输出连接到将所有PLB连接在一起的公共互连矩阵。

公开(公告)号：US20030117868A1

公开(公告)日：2003-06-26

申请号：US10321297

申请日：2002-12-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Balwant Singh

IPC: G11C007/00

CPC classification number: G11C29/50012 ,  G11C29/50

Abstract: A system for measuring a timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

Abstract translation: 用于测量两个数字信号之间的定时偏差的系统可以包括用于产生时间测量时钟的时钟发生器和用于在校正内部逻辑延迟之后将定时偏差转换为等效数字编码值的脉冲 - 数字转换器。 该系统还可以包括用于存储数字编码值的寄存器组，以及用于产生用于控制脉冲数字转换器和寄存器组的操作的控制信号和序列的控制器。

公开(公告)号：US09397622B2

公开(公告)日：2016-07-19

申请号：US14530055

申请日：2014-10-31

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03F3/45 ,  H03K5/24

CPC classification number: H03F3/45179 ,  H03F2200/129 ,  H03F2203/45112 ,  H03F2203/45116 ,  H03K5/2481

Abstract: In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

Abstract translation: 在一个实施例中，电路包括具有与第一晶体管和第二晶体管的差分对的差分放大器。 第一和第二晶体管中的每一个包括前门接触和后门接触。 第一数字反馈回路耦合在差分放大器的输出端与第一晶体管的后栅极接触之间。 第二数字反馈环耦合到第二晶体管的背栅极接触。 第一数字反馈回路被配置为与第二数字反馈回路相位相反。

公开(公告)号：US09246509B1

公开(公告)日：2016-01-26

申请号：US14474945

申请日：2014-09-02

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Neha Bhargava ,  Ankur Bal

IPC: H03M3/02 ,  H03M3/00

CPC classification number: H03M3/412 ,  H03M1/145 ,  H03M1/68 ,  H03M3/382 ,  H03M3/424 ,  H03M3/458 ,  H03M3/464

Abstract: A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.

Abstract translation: Σ-Δ模数转换器包括包括分段数模转换器（DAC）的Σ-Δ调制器，分段DAC包括粗DAC和精细DAC，其中，Σ-Δ调制器被配置为产生粗 量化信号和精细量化信号; 复合逻辑，被配置为组合所述粗量化信号和所述精细量化信号; 以及可在校准模式下操作的校准电路，以校准复合逻辑以补偿分段DAC的粗DAC和精细DAC之间的失配。

公开(公告)号：US20130205587A1

公开(公告)日：2013-08-15

申请号：US13841099

申请日：2013-03-15

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Joshipura JWALANT ,  Nitin BANSAL ,  Amit KATYAL ,  Massimiliano PICCA

IPC: H05K3/30

CPC classification number: H05K3/30 ,  G06F17/5063 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract translation: 一种用于集成电压调节器的区域有效的分布式装置，其包括耦合在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸复制品的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的外围分配所述设备的副本的轨道。 该装置作为小尺寸复制件耦合在所述第二填充单元的下部，用于将所述装置分配在所述芯片的外围并提供最大的面积利用率。

公开(公告)号：US20130128656A1

公开(公告)日：2013-05-23

申请号：US13682592

申请日：2012-11-20

Applicant: STMicroelectronics PVT LTD. ,  STMicroelectronics S.r.l.

Inventor： Danilo Rimondi ,  Carolina Selva ,  Ashish Kumar

IPC: G11C11/00

CPC classification number: G11C11/00 ,  G11C7/20 ,  G11C7/227 ,  G11C11/41 ,  G11C11/413 ,  G11C29/12015 ,  G11C29/24

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract translation: 静态随机存取存储器（SRAM）装置包括多个存储单元的存储器阵列，一个接收由一连串外部脉冲形成的外部时钟信号并产生一系列内部脉冲形成的内部时钟信号的控制器，以及 一个接收内部时钟信号的驱动电路。 控制器可在第一模式下操作，其中控制器针对每个外部脉冲产生相应的内部脉冲，并且控制器控制驱动电路，使得驱动电路对每个内部脉冲执行对存储器阵列的一次访问。 控制器还可在第二模式中操作，其中控制器针对每个外部脉冲产生一对内部脉冲，并且控制器控制驱动电路，使得对于每对内部脉冲，驱动电路写入第一数据 项目，然后读取该组存储器单元，以便获取第二数据项。

公开(公告)号：US20040239368A1

公开(公告)日：2004-12-02

申请号：US10768962

申请日：2004-01-30

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: H03K019/094

CPC classification number: G11C5/063 ,  H03K19/0019

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state. This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary line.

Abstract translation: 一种使用电荷重新分配来减少数字电路中的功耗的方法和系统，包括多条信号线，中间浮动虚拟源/宿和连接到每条所述信号线的电荷再分配电路，所述信号线将所述线与源极隔离并连接 它在状态改变之前的空闲时段期间到中间浮动虚拟源/汇。 该充电重新分配由于充电回收而不插入额外的互补线路，提供稳定的统计独立优势。

公开(公告)号：US20040167950A1

公开(公告)日：2004-08-26

申请号：US10727138

申请日：2003-12-03

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kaushik Saha ,  Srijib Narayan Maiti

IPC: G06F015/00

CPC classification number: G06F17/142

Abstract: A linear scalable method computes a Fast Fourier Transform (FFT) or Inverse Fast Fourier transform (IFFT) in a multiprocessing system using a decimation in time approach. Linear scalability means, as the number of processor increases by a factor P (for example), the computational cycle reduces by exactly the same factor P. The method includes computing the first two stages of an N-point FFT/IFFT as a single radix-4 butterfly computation operation while implementing the remaining (log2Nnull2) stages as radix-2 operations. Each radix-2 operation employs a single radix-2 butterfly computation loop without employing nested loops. The method also includes distributing the computation of the butterflies in each sage such that each processor computes an equal number of complete butterfly calculations thereby eliminating data interdependency in the stage.

Abstract translation: 线性可伸缩方法在使用时间抽取方法的多处理系统中计算快速傅里叶变换（FFT）或快速傅里叶逆变换（IFFT）。 线性可伸缩性意味着，随着处理器的数量增加因子P（例如），计算周期减少了完全相同的因子P.该方法包括将N点FFT / IFFT的前两个阶段计算为单个基数 -4蝶形计算操作，同时以基数-2操作实现剩余（log2N-2）级。 每个radix-2操作都使用单个2进制蝶形计算循环，而不使用嵌套循环。 该方法还包括在每个鼠标中分配蝴蝶的计算，使得每个处理器计算相等数量的完整蝴蝶计算，从而消除阶段中的数据相互依赖性。

公开(公告)号：US20040042139A1

公开(公告)日：2004-03-04

申请号：US10464812

申请日：2003-06-16

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Gaetano Belverde ,  Maurizio Melito ,  Salvatore Musumeci ,  Raosario Pagano ,  Angelo Raciti

IPC: H02H003/00

CPC classification number: H03K17/08128 ,  H03K17/0828

Abstract: A protection circuit for a control terminal of a power device of the type comprising at least one resistive element connected between at least one output terminal of a driver and the control terminal of the power device includes at least one turning-off transistor having its conduction terminals connected to the control terminal of the power device and to at least one output terminal of the driver, respectively. A control terminal is coupled to the control terminal of the power device through a second resistive element.

Abstract translation: 用于这种类型的功率器件的控制端子的保护电路包括连接在驱动器的至少一个输出端和功率器件的控制端之间的至少一个电阻元件，该至少一个电阻元件包括至少一个截止晶体管，其具有导通端子 分别连接到电力装置的控制端子和驱动器的至少一个输出端子。 控制端子通过第二电阻元件耦合到功率器件的控制端子。

公开(公告)号：US20040032284A1

公开(公告)日：2004-02-19

申请号：US10460044

申请日：2003-06-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.