-
公开(公告)号：JP2004153834A
公开(公告)日：2004-05-27
申请号：JP2003371563
申请日：2003-10-31
Inventor： GONTOWSKI WALTER S JR
CPC classification number: H03F3/3071 , G11B5/5526 , G11B5/59605 , G11B7/08505
Abstract: PROBLEM TO BE SOLVED: To provide an amplifier which improves a clamp operation and saturation detection and is used for a disk drive or the like. SOLUTION: The amplifier has an output stage including first and second output transistors and a bias stage for generating first and second bias voltages in control terminals of the first and second output transistors based upon a supplied voltage and an input signal of the amplifier. Besides, the amplifier includes a clamp stage equipped with first and second clamp transistors for respectively clamping outputs of the first and second output transistors to higher and lower clamp voltages. The amplifier further includes a clamp stage connected to said clamp stage for supplying a saturation signal to at least one for clamping the output of the first output transistor to the higher clamp voltage (a) and clamping the output of the second output transistor to the lower clamp voltage (b). COPYRIGHT: (C)2004,JPO
-
公开(公告)号：JP2004031912A
公开(公告)日：2004-01-29
申请号：JP2003060193
申请日：2003-03-06
Inventor： DANIEL A THOMAS , HARRY MICHAEL SIEGEL , DO BENTO VIEIRA ANTONIO A , ANTHONY M CHU
IPC: H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/12 , H01L23/31 , H01L23/485
CPC classification number: H01L24/13 , H01L23/3114 , H01L24/11 , H01L2224/0401 , H01L2224/05546 , H01L2224/05624 , H01L2224/05684 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , H01L2924/00014
Abstract: PROBLEM TO BE SOLVED: To provide an improved system and method for applying a re-distributed metal layer in an integrated circuit chip. SOLUTION: The re-distributed metal layer 260 is formed of the last metal layer in an integrated circuit in the manufacturing period of the integrated circuit before final passivation is applied. This last metal layer provides a part for a solder bump pad to be used for flip chip interconnection. The re-distributed metal layer may be stuck on (1) a flat layer stuck on the second metal layer from the last through an aperture in a dielectric layer, or (2) an array configured of a via connected to the second metal layer from the last. COPYRIGHT: (C)2004,JPO
-
公开(公告)号：JP2004025426A
公开(公告)日：2004-01-29
申请号：JP2002370549
申请日：2002-12-20
Inventor： SANTORUVO GAETANO , LO PRIORE STEFANO
IPC: B41J2/05 , B01J19/00 , B01L3/00 , B01L7/00 , B41J2/14 , B81B1/00 , B81B3/00 , H01L23/34 , H01L27/12 , H01L29/06 , H01L29/78 , H05B3/28
CPC classification number: H05B3/28 , B01J19/0093 , B01J2219/00783 , B01J2219/00873 , B01L3/5027 , B01L7/52 , B41J2/14129 , B41J2202/13 , H01L23/345 , H01L27/1203 , H01L29/0657 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a small-sized improved heater using a transistor. SOLUTION: An integrated heater formed as a field effect transistor in a semiconductor substrate 12, with the transistor having source region 14 and a drain region 16 with a channel region extending therebetween to conduct current. The channel region has a resistance R DS when conducting current to generate heat above a selected threshold. A dielectric layer 24 is disposed on the channel region 20 and a gate electrode 26 is disposed on the dielectric layer to control the current of the channel region 20. A thermally insulating barrier may be formed in the semiconductor material extending about the transistor. The object 32 to be heated is positioned to receive the heat generated by the resistance R DS of the channel region 20, and the object 32 to be heated may be a fluid chamber. COPYRIGHT: (C)2004,JPO
-
44.发明专利
公开(公告)号：JP2008290705A
公开(公告)日：2008-12-04
申请号：JP2008048164
申请日：2008-02-28
Inventor： BURLAK GARY JOSEPH , MIROWSKI MARIAN
CPC classification number: H02H3/12 , Y10T307/549
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit and a method for the classification of electrical devices.
SOLUTION: An integrated circuit device and a method for classifying electrical devices is disclosed. Reference current responses of a plurality of electrical devices are determined and stored in a memory 208. A real-time current response of a specific electrical device is measured and stored in the memory 208. A processor 204 compares the measured real-time current response of the specific electrical device to the reference current responses of the plurality of electrical devices. The classification of the electrical device is then performed based on the comparison.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供用于电气设备分类的集成电路和方法。 解决方案：公开了一种用于对电气设备进行分类的集成电路器件和方法。 确定多个电气设备的参考电流响应并将其存储在存储器208中。测量特定电气设备的实时电流响应并将其存储在存储器208中。处理器204将测量的实时电流响应与 所述特定电气设备与所述多个电气设备的参考电流响应相关。 然后根据比较进行电气设备的分类。 版权所有（C）2009，JPO＆INPIT
-
45.发明专利Integrated circuit and method for monitoring and controlling power and sensing open load state 审中-公开集成电路和监控和控制开关负载状态的方法
公开(公告)号：JP2008275590A
公开(公告)日：2008-11-13
申请号：JP2008047805
申请日：2008-02-28
Inventor： BURLAK GARY JOSEPH , MIROWSKI MARIAN
CPC classification number: H02H3/12 , Y10T307/549
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit and a method for monitoring and controlling power, and identifying an open circuit state at an output port. SOLUTION: The minimum open circuit current value at the output port is stored in a memory 208. An average of the current is calculated in a steady state by a current detecting circuit 216. The calculated average and the minimum open circuit current value are compared. The open circuit state at the output port is determined based on a comparison result. A determination result is transmitted to a power control circuit 212. The power control circuit 212 implements a required control. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供一种集成电路和用于监视和控制电力的方法，以及识别输出端口处的开路状态。 解决方案：输出端口处的最小开路电流值存储在存储器208中。电流检测电路216在稳定状态下计算电流的平均值。所计算出的平均和最小开路电流值 被比较。 基于比较结果确定输出端口处的开路状态。 确定结果被发送到功率控制电路212.功率控制电路212执行所需的控制。 版权所有（C）2009，JPO＆INPIT
-
Patent Agency Ranking46.发明专利Integrated circuit, and method for preserving charge of battery for vehicle and for protecting trailer load thereof 有权集成电路和用于保存车辆电池充电和保护拖车的负载的方法
公开(公告)号：JP2008245511A
公开(公告)日：2008-10-09
申请号：JP2008047974
申请日：2008-02-28
Inventor： BURLAK GARY JOSEPH , MIROWSKI MARIAN
CPC classification number: H02H3/12 , Y10T307/549
Abstract: PROBLEM TO BE SOLVED: To provide a method for preserving charge of a battery as well as protecting electrical devices, and to provide an integrated circuit. SOLUTION: A maximum and a minimum battery voltage values at an output port are stored in a memory. A steady-state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady-state battery voltage with the maximum and the minimum battery voltage values. When the measured steady state battery voltage value is greater than the maximum battery voltage value, overvoltage state is reported by the processor. When the measured steady-state battery voltage value is smaller than the minimum battery voltage value, low battery voltage state is reported by the processor. COPYRIGHT: (C)2009,JPO&INPIT
Abstract translation: 要解决的问题：提供一种保存电池的电荷以及保护电气装置的方法，并提供集成电路。
解决方案：输出端口的最大和最小电池电压值存储在存储器中。 输出端口的稳态电池电压被测量并存储在存储器中。 处理器将测量的稳态电池电压与最大和最小电池电压值进行比较。 当测量的稳态电池电压值大于最大电池电压值时，处理器报告过电压状态。 当测量的稳态电池电压值小于最小电池电压值时，处理器报告电池电压低的状态。 版权所有（C）2009，JPO＆INPIT
-
47.发明专利Method and apparatus for efficient and flexible sequencing of data processing unit extending vliw architecture 审中-公开数据处理单元有效和灵活地排序扩展VLIW架构的方法与装置
公开(公告)号：JP2006221624A
公开(公告)日：2006-08-24
申请号：JP2006017695
申请日：2006-01-26
Inventor： DASH DILLIP K
CPC classification number: G06F9/325 , G06F9/30065 , G06F9/3853 , G06F9/3885
Abstract: PROBLEM TO BE SOLVED: To provide an improved very long instruction word processor with sequence control. SOLUTION: During each cycle, this processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based on that instruction. The instruction set further includes flow control instructions enabling repetitive execution of a single instruction, repetitive execution of a block comprising a plurality of instructions or branching within a program. Such a processor can be used in connection with a disk controller for a hard drive of a computer. The flexible sequencing allows a hard-drive controller to be readily reprogrammed for use in connection with different types of media or to be dynamically reprogrammed upon detection of a disk read error to increase the ability of the disk controller to recover data from a disk. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供具有序列控制的改进的非常长的指令字处理器。 解决方案：在每个周期中，该处理器根据指令字段中的值产生对功能单元的控制信号。 每个指令可以包括指定基于该指令来生成控制信号的周期数的迭代计数。 指令集进一步包括能够重复执行单个指令的流控制指令，包括多个指令或程序内的分支的块的重复执行。 这种处理器可以与用于计算机的硬盘驱动器的盘控制器结合使用。 灵活的排序允许硬盘驱动器控制器被轻易地重新编程以用于与不同类型的介质相关联，或者在检测到磁盘读取错误时被动态重新编程，以增加磁盘控制器从磁盘恢复数据的能力。 版权所有（C）2006，JPO＆NCIPI
-
48.发明专利
公开(公告)号：JP2005184829A
公开(公告)日：2005-07-07
申请号：JP2004365275
申请日：2004-12-17
Inventor： DANG PHILIP
CPC classification number: H04N19/436 , H04N19/42 , H04N19/60
Abstract: PROBLEM TO BE SOLVED: To provide an integer transform processing technology wherein computational complexity is reduced. SOLUTION: First and second integer transform matrices can be used to approximate the discrete cosine transform. An input matrix of data is multiplied by a first transform matrix of integers to produce an intermediate matrix of data. The intermediate matrix is multiplied by a second transform matrix of integers to produce a transform result matrix of data. The multiplications by the first and second transform matrices can be pipelined to increase throughput. A plurality of transform data paths can also be provided in parallel to increase throughput. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种降低计算复杂度的整数变换处理技术。 解决方案：可以使用第一和第二整数变换矩阵近似离散余弦变换。 数据的输入矩阵乘以整数的第一变换矩阵以产生数据的中间矩阵。 将中间矩阵乘以第二个整数变换矩阵以产生数据的变换结果矩阵。 第一和第二变换矩阵的乘法可以被流水线化以增加吞吐量。 还可以并行提供多个变换数据路径以增加吞吐量。 版权所有（C）2005，JPO＆NCIPI
-
49.发明专利Composite camera and method for achieving automatic focusing, depth of field, and high resolution function 审中-公开用于实现自动聚焦，现场深度和高分辨率功能的复合摄像机和方法
公开(公告)号：JP2004312745A
公开(公告)日：2004-11-04
申请号：JP2004110671
申请日：2004-04-05
Inventor： CHEN GEORGE Q , HONG LI , MCGUINNESS PETER
CPC classification number: H04N5/247 , G06K9/209 , G06T15/20 , G06T2200/21 , G06T2207/10052 , H04N5/23232
Abstract: PROBLEM TO BE SOLVED: To provide a composite camera system for generating an improved virtual image having a large depth of field.
SOLUTION: This system has a plurality of component cameras for generating image data of an object and a data processor for generating an improved virtual image from the image data. The data processor generates a first component virtual image form a first depth face, generates a second component virtual image from a second depth face and generates the improved virtual image by inserting a first pixel selected from the first component virtual image into the improved virtual image and inserting a second pixel selected from the second component virtual image into the improved virtual image.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供一种用于生成具有大景深的改进的虚像的复合照相机系统。 解决方案：该系统具有多个用于生成对象的图像数据的分量摄像机和用于从图像数据生成改进的虚像的数据处理器。 数据处理器从第一深度面生成第一分量虚拟图像，从第二深度面产生第二分量虚拟图像，并通过将从第一分量虚拟图像中选择的第一像素插入改进的虚拟图像并生成改进的虚拟图像，以及 将从所述第二分量虚拟图像中选择的第二像素插入到所述改进的虚像中。 版权所有（C）2005，JPO＆NCIPI
-
50.发明专利
公开(公告)号：JP2004310777A
公开(公告)日：2004-11-04
申请号：JP2004110729
申请日：2004-04-05
Inventor： CHEN GEORGE Q , HONG LI , MCGUINNESS PETER
CPC classification number: G06K9/209 , G06T5/003 , G06T5/50 , G06T15/20 , G06T2207/10028 , H04N5/2258 , H04N5/23229
Abstract: PROBLEM TO BE SOLVED: To provide a combination camera system and a method for compositing a virtual image from a plurality of inputted images. SOLUTION: The combination camera system has a plurality of component cameras and a processor. The processor receives first image data from a first camera, receives second image data from a second camera and generates the virtual image from them. In addition, the processor generates point data (x, y, z) located at depth z=Z1 of an object surface of an object by projecting virtual pixel data (u, v) and generates first pixel data (u 1 , v 1 ) located on an image surface of a first image by projecting the point data (x, y, z). COPYRIGHT: (C)2005,JPO&NCIPI
-
-
-
-
-
-
-
-
-
Search Results
3135
records
(took 0.067 seconds)
