公开(公告)号：US20040120385A1

公开(公告)日：2004-06-24

申请号：US10632566

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20030158882A1

公开(公告)日：2003-08-21

申请号：US10322197

申请日：2002-12-17

Applicant: STMicroelectronics Limited

Inventor： Simon Knowles

IPC: G06F007/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimized. For bit lengths n, the number (mnull2) of logical stages is nnull2mnull1 and for bit lengths n not of a binary order, the number (mnull2) of logical stages is nbonull2mnull1, where nbo is the next largest binary order after n.

Abstract translation: 描述了根据该方法设计的加法电路的设计方法和加法电路。 优化设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数和通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。 对于位长度n，逻辑级数（m + 2）为n = 2m + 1，对于不是二进制顺序的位长度n，逻辑级的数量（m + 2）为nbo = 2m + 1，其中 nbo是n之后的下一个最大的二进制顺序。

公开(公告)号：US20030140338A1

公开(公告)日：2003-07-24

申请号：US10206381

申请日：2002-07-26

Applicant: STMicroelectronics Limited

Inventor： Antony Bowers ,  Richard Shann

IPC: G06F009/44

CPC classification number: G06F8/54

Abstract: Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequences of instructions that describe how the current call frame changes during execution of each function. Described herein is a means of generating call frame information at link time, using linker macro calls generated by a small set of assembler macros.

Abstract translation: 呼叫帧信息由调试软件使用。 它记录了在执行程序期间的任何时候如何恢复父堆栈帧。 它通常在编译期间生成并以压缩格式存储在可执行文件中，该格式由描述当前调用帧在每个功能执行期间如何改变的指令序列组成。 这里描述的是使用由一组汇编器宏生成的链接器宏调用在链接时产生呼叫帧信息的手段。

公开(公告)号：US20030068000A1

公开(公告)日：2003-04-10

申请号：US10247263

申请日：2002-09-18

Applicant: STMicroelectronics Limited

Inventor： Robert Geoffrey Warren

IPC: G06F003/00 ,  H04L007/00

CPC classification number: G01R31/318552 ,  G01R31/31937

Abstract: A system comprising a host, a target and connection means therebetween. The host has means for providing a clock signal, first output means for outputting said clock signal to said target via said connection means and second output means for outputting data to said target via said connection means, said data being clocked out by said clock signal, said target having first input means for receiving said clock signal from said host, second input means for receiving said data from said host and first output means for outputting data to said host via said connection means. The host further comprises input means for receiving said data from said target, and oversampling means for oversampling the received data from the target and controlling the clocking in of said data received from said target in dependence on said oversampling.

Abstract translation: 一种包括主机，目标和它们之间的连接装置的系统。 主机具有用于提供时钟信号的装置，用于经由所述连接装置将所述时钟信号输出到所述目标的第一输出装置和用于经由所述连接装置将数据输出到所述目标的第二输出装置，所述数据由所述时钟信号输出， 所述目标具有用于从所述主机接收所述时钟信号的第一输入装置，用于从所述主机接收所述数据的第二输入装置和用于经由所述连接装置向所述主机输出数据的第一输出装置。 主机还包括用于从所述目标接收所述数据的输入装置，以及过采样装置，用于对来自目标的接收数据进行过采样，并根据所述过采样来控制从所述目标接收的所述数据的时钟。

公开(公告)号：US20030016836A1

公开(公告)日：2003-01-23

申请号：US10147436

申请日：2002-05-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: H04B015/00

CPC classification number: H03G3/345 ,  H03G3/34

Abstract: A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio signal prior to its application to the input node, and a further bipolar transistor is connected between the FET and the output node for raising the voltage level of the audio signal prior to its application to the output node. This serves to maintain the DC bias level of the audio output signal independently of the status of the mute control signal.

Abstract translation: 一种静音开关，包括场效应晶体管，在其栅极处接收静音控制信号，用于选择性地将音频信号从输入节点提供给输出节点。 双极晶体管连接在输入节点和FET之间，用于在施加到输入节点之前降低音频信号的电压电平，并且在FET和输出节点之间连接另外的双极晶体管，以提高电压电平 该音频信号在其应用于输出节点之前。 这用于独立于静音控制信号的状态来维持音频输出信号的DC偏置电平。

公开(公告)号：US20030011592A1

公开(公告)日：2003-01-16

申请号：US10133971

申请日：2002-04-26

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Magne Sandven

IPC: G06T017/00

CPC classification number: G06T15/005

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract translation: 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

公开(公告)号：US20020171459A1

公开(公告)日：2002-11-21

申请号：US10104994

申请日：2002-03-22

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: H03K021/00

CPC classification number: H03K23/68 ,  H03K23/546

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract translation: 数字分频器包括以输入频率的整个或半个周期为增量的输出信号的相位控制。 通过改变（逻辑上或物理上）通过加载位模式的移位寄存器的抽头点进行适当划分来实现整个周期相位控制。 半周期相位变化通过多路复用器每半周期选择两个信号之一来实现。

公开(公告)号：US20020131298A1

公开(公告)日：2002-09-19

申请号：US10085987

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： William Bryan Barnes

IPC: G11C011/34

CPC classification number: H03K5/249 ,  G11C7/065 ,  H03K3/356139 ,  H03K5/1534 ,  H03K19/0963

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated. A differential offset dynamic comparator and timing circuit are used to evaluate whether the node is being discharged. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract translation: 为了确定预充电节点是否保持隔离或者可替代地进行放电，常规电路允许不确定性。 在评估开始一段时间后，常规电路将给出一个可能随后证明是错误的初步结果。 评估过程中耗电。 差分偏移动态比较器和定时电路用于评估节点是否正在放电。 由于比较器具有偏移，因此可以感测到与预充电电位相差较小的偏差：因为它是动态的，所以它不消耗稳态电流。 定时电路可以准确了解何时查看输出：在定时周期过去之前，已知结果无效。

公开(公告)号：US20040233911A1

公开(公告)日：2004-11-25

申请号：US10794581

申请日：2004-03-05

Applicant: STMICROELECTRONICS LIMITED

Inventor： Matt Morris

IPC: H04L012/28

CPC classification number: H04J3/0632 ,  H04J3/0685

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values that are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract translation: 描述了流处理系统，其中输入流的分组各自包括表示分组之间的相对延迟的各个时间戳。 可编程计数器产生与分组流中的时间戳相比较的连续计数值。 输出控制器基于比较的结果来确定是否从输出端口释放分组，优选地仅当可编程计数值等于时间戳时才释放分组。

公开(公告)号：US20040228342A1

公开(公告)日：2004-11-18

申请号：US10779466

申请日：2004-02-16

Applicant: STMicroelectronics Limited

Inventor： Matt Morris

IPC: H04L012/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，特别是将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。