Abstract:
A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
Abstract:
A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
Abstract:
A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.
Abstract:
A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
Abstract:
The present invention relates to a method for preparing an itraconazole-containing solid dispersion. The itraconazole-containing solid dispersion according to the preparing method of the present invention has both improved solubility and rapid dissolution rate so that it has an excellent bioavailability. The itraconazole-containing solid dispersion of the present invention is also independent of pH variation of human stomach so that it can minimize the absorption variation of intra- and inter-individuals. In addition, the itraconazole-containing solid dispersion according to the preparing method of the present invention is stable for a long time. The present invention also provides an economical and environment-friendly method for manufacturing an itraconazole-containing composition because the method adds a lactic acid in a solution comprising itraconazole to decrease the amount of an organic solvent needed to dissolve itraconazole.
Abstract:
Provided are a user authentication method and an electronic device performing the method. The method is performed under the control of a processor and includes inputting a user authentication request for identifying a user, generating random number data that corresponds to knowledge-based authentication information in the user authentication request, generating an authentication code by combining biometrics-based authentication information in the user authentication request and the random number data, and processing the user authentication request based on the authentication code.
Abstract:
Disclosed is a load limiter mounted within a cylindrical spool on which a webbing is wound to constrain a load applied to the webbing from exceeding a preset load, the load limiter including: a first torsion bar inserted into a hollow portion formed at a center of the spool and one end of which is coupled to one end of the spool; and a second torsion bar one end of which is connected to an opposite end of the first torsion bar to be inserted into the hollow portion of the spool together with the first torsion bar and an opposite end of which is coupled to a locker installed at an opposite end of the spool, wherein the torsion bar is configured such that a torsion load limit of the first torsion bar is smaller than a torsion load limit of the second torsion bar.
Abstract:
The manufacturing method for high-purity Zirconium is characterized by self-propagating high temperature synthesis (SHS) of a raw material having zirconium raw ore containing ZrO2, ZrSiO4, KZr2(PO4)3, or a mixture thereof and a reducing agent that is metal powder, to prepare zirconium intermetallic compound or zirconium nitride, followed by the recovery of high-purity Zr by electrolytic refining the reaction product of the SHS.
Abstract:
Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.