MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM
    44.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, METHOD OF OPERATING MEMORY DEVICE, AND METHOD OF OPERATING MEMORY SYSTEM 有权
    存储器件,存储器系统,操作存储器件的方法和操作存储器系统的方法

    公开(公告)号:US20170062059A1

    公开(公告)日:2017-03-02

    申请号:US15245162

    申请日:2016-08-23

    Abstract: A memory device, comprising: a memory cell array including a plurality of NAND strings, each NAND string including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate; and a control logic configured to generate a pre-programming control signal for memory cells of a first NAND string of the NAND strings such that, before erasing the memory cells of the first NAND string, pre-programming voltages applied to the word lines coupled to the corresponding memory cells of the first NAND string vary based on an operating characteristic of the corresponding memory cells.

    Abstract translation: 一种存储器件,包括:包括多个NAND串的存储单元阵列,每个NAND串包括分别连接到垂直堆叠在衬底上的多个字线的多个存储器单元; 以及控制逻辑,被配置为为NAND串的第一NAND串的存储器单元生成预编程控制信号,使得在擦除第一NAND串的存储单元之前,将预编程电压施加到耦合到 第一NAND串的对应存储单元基于相应的存储单元的工作特性而变化。

    NONVOLATILE MEMORY DEVICE
    45.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号:US20170011799A1

    公开(公告)日:2017-01-12

    申请号:US14996249

    申请日:2016-01-15

    Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

    Abstract translation: 非易失性存储器包括存储单元阵列,行解码器电路和页缓冲电路。 行解码器电路响应于从外部设备接收到的写入命令,在第一预充电操作时,对连接到所选存储块的串选择晶体管的串选择线施加导通电压。 页缓冲器电路响应于写入命令,在第一预充电操作下,连接到串选择晶体管的第一电压至位线,而不管加载数据如何,并施加第一电压和 基于所加载的数据,在第二预充电操作中通过第二预充电电路对位线施加第二电压。 在第一预充电操作期间,写数据被加载到页缓冲电路。

    Load limiter
    48.
    发明授权
    Load limiter 有权
    负载限制器

    公开(公告)号:US09283928B2

    公开(公告)日:2016-03-15

    申请号:US14000719

    申请日:2012-01-30

    CPC classification number: B60R22/341 B60R22/3413

    Abstract: Disclosed is a load limiter mounted within a cylindrical spool on which a webbing is wound to constrain a load applied to the webbing from exceeding a preset load, the load limiter including: a first torsion bar inserted into a hollow portion formed at a center of the spool and one end of which is coupled to one end of the spool; and a second torsion bar one end of which is connected to an opposite end of the first torsion bar to be inserted into the hollow portion of the spool together with the first torsion bar and an opposite end of which is coupled to a locker installed at an opposite end of the spool, wherein the torsion bar is configured such that a torsion load limit of the first torsion bar is smaller than a torsion load limit of the second torsion bar.

    Abstract translation: 公开了一种安装在圆柱形卷轴内的负载限制器,其上缠绕有织带以限制施加到织带上的负载超过预设的负载,该负载限制器包括:第一扭杆,插入形成在中心部分的中空部分 阀芯,其一端连接到阀芯的一端; 以及第二扭杆,其一端连接到所述第一扭杆的相对端,以与所述第一扭杆一起插入所述卷轴的中空部分中,并且其相对端连接到安装在所述第一扭杆上的储物柜 所述卷轴的相对端部,其中所述扭杆被构造成使得所述第一扭杆的扭转载荷极限小于所述第二扭杆的扭转载荷极限。

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