公开(公告)号：US20070185670A1

公开(公告)日：2007-08-09

申请号：US11733220

申请日：2007-04-10

Applicant: Hyun-Jin Kim ,  Sang-Bo Lee

Inventor： Hyun-Jin Kim ,  Sang-Bo Lee

IPC: G01R23/00

CPC classification number: G11C7/22 ,  G11C7/16 ,  G11C7/222

Abstract: A method of measuring a frequency of an input clock signal may include generating an output pulse responsive to an edge of the input clock signal, and charging an electrical circuit responsive to the output pulse. An analog output signal may be generated responsive to the charged electrical circuit, and the analog output signal may be converted into a digital value representing a frequency of the input clock signal. Related frequency measuring circuits and memory devices are also discussed.

Abstract translation: 测量输入时钟信号的频率的方法可以包括响应于输入时钟信号的边缘产生输出脉冲，以及响应于输出脉冲对电路充电。 可以响应于充电的电路产生模拟输出信号，并且模拟输出信号可以被转换成表示输入时钟信号的频率的数字值。 还讨论了相关的频率测量电路和存储器件。

公开(公告)号：US07065003B2

公开(公告)日：2006-06-20

申请号：US11188708

申请日：2005-07-26

Applicant: Sang-bo Lee ,  Ho-young Song

Inventor： Sang-bo Lee ,  Ho-young Song

IPC: G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2281

Abstract: The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

Abstract translation: 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间信息选择性地将至少一个传送信号与至少一个采样信号相关联，以在相关联的采样和传输信号之间产生期望的时序关系。 延迟电路根据至少一个采样信号存储读取信息，并且基于与用于存储读取的信息的采样信号相关联的传送信号产生等待时间信号。

公开(公告)号：US20060077751A1

公开(公告)日：2006-04-13

申请号：US11202314

申请日：2005-08-12

Applicant: Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

Inventor： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

IPC: G11C8/02

CPC classification number: G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

Abstract: In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

Abstract translation: 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

公开(公告)号：US20060028888A1

公开(公告)日：2006-02-09

申请号：US11188184

申请日：2005-07-20

Applicant: Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

Inventor： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC: G11C7/00

CPC classification number: G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

Abstract translation: 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US06914829B2

公开(公告)日：2005-07-05

申请号：US10815574

申请日：2004-04-01

Applicant: Sang-bo Lee

Inventor： Sang-bo Lee

IPC: G11C11/40 ,  G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C7/106 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072

Abstract: An output multiplexing circuit for a Double Data Rate (DDR) synchronous memory device includes n first latches, n first switches, n second switches, n second latches, and two third switches. The n first latches simultaneously prefetch n-bit data transmitted from a memory cell array via a data path. The n first switches simultaneously transfer the n-bit data prefetched into the first latches to n nodes in response to a CAS latency information signal. The n second switches simultaneously transfer data on the nodes in response to n signals that are synchronized with a clock signal and sequentially generated at a predetermined interval. The n second latches store the data transferred via the second switches. The two third switches sequentially transfer the data stored in the n second latches to an input terminal of an output driver of the memory device at a rising edge and a falling edge of a delay signal of the clock signal. Analogous methods also are described.

Abstract translation: 一种用于双倍数据速率（DDR）同步存储器件的输出复用电路包括n个第一锁存器，n个第一开关，n个第二开关，n个第二锁存器和两个第三开关。 n个第一锁存器同时预取通过数据路径从存储器单元阵列发送的n位数据。 响应于CAS延迟信息信号，n个第一交换机同时将预取到第一锁存器的n位数据传送到n个节点。 响应于与时钟信号同步并以预定间隔顺序产生的n个信号，n个第二切换器同时传送节点上的数据。 n个第二个锁存器存储通过第二个开关传送的数据。 两个第三开关在时钟信号的延迟信号的上升沿和下降沿，将存储在n个第二锁存器中的数据顺序地传送到存储器件的输出驱动器的输入端。 还描述了类似的方法。

公开(公告)号：US06329854B1

公开(公告)日：2001-12-11

申请号：US09387376

申请日：1999-08-31

Applicant: Sang-bo Lee ,  Jae-hyoong Lee

Inventor： Sang-bo Lee ,  Jae-hyoong Lee

IPC: H03L706

CPC classification number: H03L7/10 ,  H03L7/0814 ,  H03L7/0891

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device. The variable delay line may contain a string of unit delay devices and a string of switches that each have an input electrically coupled to an output of a corresponding unit delay device. Each of the unit delay devices in the string may provide a fixed delay or a variable delay that is influenced (e.g., increased) by changes (e.g., increases) in the magnitude of the phase control signal VCON.

Abstract translation: 锁相环集成电路包括相位检测电路，可变延迟器件和延迟控制电路。 可变延迟装置和延迟控制电路通过以优选的方式增加延迟锁定环集成电路的信号频率带宽来提供改进的特性。 相位检测电路被配置为执行比较第一和第二周期信号的功能，并且产生具有与第一和第二周期信号之间的相位差成比例的第一属性（例如，幅度）的相位控制信号（例如，VCON） 周期信号。 延迟控制电路响应相位控制信号VCON并产生提供给可变延迟装置的延迟控制信号。 延迟控制电路可以包括计数器，第一比较器，第二比较器和移位寄存器。 可变延迟装置包括可变延迟线和补偿延迟装置。 可变延迟线可以包含一串单位延迟装置和一串开关，每个开关具有电耦合到对应的单位延迟装置的输出的输入。 串中的每个单元延迟装置可以通过相位控制信号VCON的大小的改变（例如，增加）来提供固定的延迟或可变延迟。

公开(公告)号：US06232813B1

公开(公告)日：2001-05-15

申请号：US09419837

申请日：1999-10-15

Applicant: Sang-bo Lee

Inventor： Sang-bo Lee

IPC: H04L708

CPC classification number: H03L7/0814 ,  H03K5/133

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON1) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON1 and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device. The variable delay line may contain a string of unit delay devices and a string of switches that each have an input electrically coupled to an output of a corresponding unit delay device. Each of the unit delay devices in the string may provide a fixed delay or a variable delay that is influenced (e.g., increased) by changes (e.g., increases) in the magnitude of the phase control signal VCON1.

Abstract translation: 锁相环集成电路包括相位检测电路，可变延迟器件和延迟控制电路。 可变延迟装置和延迟控制电路通过以优选的方式增加延迟锁定环集成电路的信号频率带宽来提供改进的特性。 相位检测电路被配置为执行比较第一和第二周期信号的功能，并产生具有与第一和第二周期信号之间的相位差成比例的第一属性（例如，幅度）的相位控制信号（例如，VCON1） 周期信号。 延迟控制电路响应于相位控制信号VCON1，并产生提供给可变延迟装置的延迟控制信号。 延迟控制电路可以包括计数器，第一比较器，第二比较器和移位寄存器。 可变延迟装置包括可变延迟线和补偿延迟装置。 可变延迟线可以包含一串单位延迟装置和一串开关，每个开关具有电耦合到相应的单位延迟装置的输出的输入。 串中的每个单元延迟装置可以通过相位控制信号VCON1的幅度的改变（例如，增加）来提供固定延迟或可变延迟。

公开(公告)号：US6094375A

公开(公告)日：2000-07-25

申请号：US223541

申请日：1998-12-30

Applicant: Sang-bo Lee

Inventor： Sang-bo Lee

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/413 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1012 ,  G11C7/1015 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C2207/107

Abstract: Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) electrically coupled to the first and second memory cell arrays, respectively. Decoder and data transmission circuits are provided and these circuits are responsive to the mode select signal and column address signals. These circuits enable operation in both single and dual data rate modes and perform the functions of simultaneously transferring read data on the first and second global input/output lines to first and second data lines, respectively, during a first read time interval when a first column address signal is in a first logic state and simultaneously transferring read data on said first and second global input/output lines to the second and first data lines, respectively, during a second read time interval when the first column address signal is in a second logic state opposite the first logic state.

Abstract translation: 可以以单数据速率模式和双数据速率模式（取决于模式选择信号的值）可操作的集成电路存储器件包括第一和第二存储单元阵列以及第一和第二全局输入/输出信号线（GIOF，GIOS） 耦合到第一和第二存储单元阵列。 提供了解码器和数据传输电路，并且这些电路响应于模式选择信号和列地址信号。 这些电路使得能够在单数据速率模式和双数据速率模式下操作，并且执行在第一读取时间间隔期间在第一读取时间间隔期间分别将第一和第二全局输入/输出线上的读取数据传送到第一和第二数据线的功能， 地址信号处于第一逻辑状态，并且当第一列地址信号处于第二逻辑时，分别在第二读取时间间隔期间将所述第一和第二全局输入/输出线上的读取数据传送到第二和第一数据线 状态与第一个逻辑状态相反。