公开(公告)号：US20080125033A1

公开(公告)日：2008-05-29

申请号：US11944695

申请日：2007-11-26

Applicant: Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

Inventor： Seong Jae Lee ,  Mi Ja Lee ,  Chang Soon Kim ,  Hyeong Soo Choi

IPC: H04B7/14

CPC classification number: H04B7/15585

Abstract: The present invention relates to a Radio Frequency Repeater to prevent oscillation with canceling a feedback interference signal between transmitting and receiving antenna with built-in transmitting and receiving antenna in wireless mobile communication repeater.A radio frequency repeater for canceling a feedback interference signal has a downlink path from a base station to a terminal and an uplink path from a terminal to a base station, and said downlink path and said uplink path is separated and combination by a duplexer.

Abstract translation: 本发明涉及一种无线电频率中继器，用于在无线移动通信中继器中利用内置发射和接收天线消除发射和接收天线之间的反馈干扰信号来防止振荡。 用于消除反馈干扰信号的射频中继器具有从基站到终端的下行链路路径和从终端到基站的上行链路路径，并且所述下行链路路径和所述上行链路路径被双工器分离并组合。

公开(公告)号：US20080121868A1

公开(公告)日：2008-05-29

申请号：US11800914

申请日：2007-05-08

Applicant: Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

Inventor： Moon-Gyu Jang ,  Yark-Yeon Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Tae-Youb Kim ,  Seong-Jae Lee

IPC: H01L29/47 ,  H01L21/338

CPC classification number: H01L29/8126 ,  H01L29/66409

Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

Abstract translation: 肖特基势垒隧道晶体管包括栅极电极和源极和漏极区域。 栅电极形成在衬底的沟道区上，以与衬底形成肖特基结。 源极和漏极区域形成在暴露于栅电极两侧的衬底中。

公开(公告)号：US07195962B2

公开(公告)日：2007-03-27

申请号：US10833452

申请日：2004-04-27

Applicant: Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

Inventor： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im ,  Chang Geun Anh

IPC: H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/28114 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66772

Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.

Abstract translation: 提供了具有超短沟道长度的MOSFET及其制造方法。 超短沟道MOSFET具有三维结构的硅线沟道区，以及形成在由硅线沟道区的两侧形成的硅导电层中的源极/漏极结。 此外，包括在其间具有高介电常数的栅极绝缘层，以及连接到源极/漏极结的源极和漏极，形成在硅线沟道区的上表面上的栅电极。 通过利用取决于硅的平面取向的不同蚀刻速率，硅线沟道区域形成有三角形或梯形截面。 源极/漏极结通过固态扩散方法形成。

公开(公告)号：US06999772B2

公开(公告)日：2006-02-14

申请号：US10452633

申请日：2003-06-03

Applicant: Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

Inventor： Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

IPC: H04Q7/20

CPC classification number: H04W72/0466 ,  H04B17/318 ,  H04B17/382 ,  H04B2201/70702 ,  H04W16/14 ,  H04W28/26 ,  H04W52/0206 ,  H04W72/02 ,  H04W72/0453 ,  H04W72/082 ,  H04W76/10 ,  H04W84/042 ,  Y02D70/00

Abstract: A method for assigning a channel in multi-FA CDMA mobile communication system according to the received power prevents communication quality of a FA from being inferior to that of the others by managing the interference level of the FA. The method comprises the steps of: comparing a first threshold value with received power when the base station receives a new call request; assigning a traffic channel in a first FA of the request, if the received power is less than the first threshold value, and searching a second FA of which received power is least, if not; comparing a second threshold value with the received power of the second FA; and assigning a traffic channel in the second FA if the received power is less than the second threshold value, and rejecting the request, if not.

公开(公告)号：US06995452B2

公开(公告)日：2006-02-07

申请号：US10749749

申请日：2003-12-30

Applicant: Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

Inventor： Wonju Cho ,  Seong Jae Lee ,  Jong Heon Yang ,  Jihun Oh ,  Kiju Im

IPC: H01L29/00

CPC classification number: H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused. Therefore, no crystal defect of a substrate is caused, thereby decreasing a junction leakage current.

Abstract translation: 提供了具有纳米级沟道的SOI MOSFET器件，其具有包括通过固相扩散形成的浅扩展区域和深结区域的源极/漏极区域以及SOI MOSFET器件的制造方法。 在制造MOSFET器件的方法中，使用掺杂有不同杂质的第一和第二氧化硅膜同时形成形成源/漏区的浅延伸区域和深结区域。 可以通过调整掺杂有第二杂质的第二氧化硅膜的厚度和蚀刻速率来缩小器件的有效沟道长度。 在形成栅电极之前，在衬底上形成源极/漏极区，从而容易地控制沟道中的杂质分布。 可以省略源极/漏极区域的杂质活化处理，从而防止器件的阈值电压的变化。 固相杂质扩散。 因此，不会引起衬底的晶体缺陷，从而减小结漏电流。

公开(公告)号：US06723587B2

公开(公告)日：2004-04-20

申请号：US10331568

申请日：2002-12-31

Applicant: Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

Inventor： Won-Ju Cho ,  Jong-Heon Yang ,  Moon-Gyu Jang ,  Seong-Jae Lee ,  Kyoung-Wan Park ,  Ki-Ju Im ,  Ji-Hun Oh

IPC: H01L2184

CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78609

Abstract: An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.

Abstract translation: 提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。 该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分 第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质 在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层 形成，形成接触孔以露出栅电极，源极区和漏极 区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

公开(公告)号：US06638823B2

公开(公告)日：2003-10-28

申请号：US09975963

申请日：2001-10-15

Applicant: Wonju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

Inventor： Wonju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

IPC: H01L218242

CPC classification number: H01L29/78642 ,  H01L27/1203 ,  Y10S977/712 ,  Y10S977/721 ,  Y10S977/723 ,  Y10S977/887

Abstract: The present invention relates to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate. To begin with, a first silicon conductive layer is formed by doping an impurity of a high concentration into a first single crystal silicon layer. Thereafter, a second single crystal silicon layer with the impurity of a low concentration and a second silicon conductive layer with the impurity of the high concentration are formed on the first silicon conductive layer. The second single crystal silicon layer and the second silicon conductive layer are vertically patterned into a predetermined configuration. Subsequently, a gate insulating layer is formed on entire surface. Then, an annealing process is carried out to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source region, a drain region and a vertical channel. Finally, a gate electrode is formed on side walls of the vertical channel.

Abstract translation: 本发明涉及具有垂直沟道和源极/漏极结构的超小尺寸垂直MOSFET器件及其通过使用绝缘体上硅（SOI）衬底制造的方法。 首先，通过将高浓度的杂质掺杂到第一单晶硅层中来形成第一硅导电层。 此后，在第一硅导电层上形成具有低浓度杂质的第二单晶硅层和具有高浓度杂质的第二硅导电层。 将第二单晶硅层和第二硅导电层垂直图案化成预定构造。 随后，在整个表面上形成栅极绝缘层。 然后，进行退火处理，以将第一硅导电层和第二硅导电层中的杂质扩散到第二单晶层中，从而形成源极区，漏极区和垂直沟道。 最后，在垂直通道的侧壁上形成栅电极。

公开(公告)号：US5994714A

公开(公告)日：1999-11-30

申请号：US932189

申请日：1997-09-17

Applicant: Kyoung Wan Park ,  Seong Jae Lee ,  Min Cheol Shin

Inventor： Kyoung Wan Park ,  Seong Jae Lee ,  Min Cheol Shin

IPC: H01L29/06 ,  H01L21/335 ,  H01L29/66 ,  H01L29/772 ,  H01L29/80 ,  H01L29/775 ,  H01L29/778

CPC classification number: B82Y10/00 ,  H01L29/66446 ,  H01L29/66977 ,  H01L29/772 ,  Y10S438/962

Abstract: The present invention discloses a technique for applying diffraction characteristic of electrons to a two-dimensional electronic device to manufacture multi-functional transistor having various ON/OFF states. A quantum diffraction transistor according to the present invention is capable of adjusting the amplitude of drain current and having various ON/OFF states utilizing diffraction characteristic of electrons by interposing a reflection-type diffraction grating in an electron path. The inventive multi-functional quantum diffraction transistor uses a two dimensional electron gas in formed at a different species junction in a semiconductor heterostructure, and has a bent electron path between the source electrode and the drain electrode with a reflection-type diffraction grating. The quantum diffraction effect of the electrons is used for the control of the diffracted drain current.

Abstract translation: 本发明公开了一种将电子衍射特性应用于二维电子器件以制造具有各种ON / OFF状态的多功能晶体管的技术。 根据本发明的量子衍射晶体管能够通过在电子路径中插入反射型衍射光栅来利用电子的衍射特性来调节漏极电流的振幅并具有各种导通/截止状态。 本发明的多功能量子衍射晶体管使用在半导体异质结构中的不同物质结处形成的二维电子气体，并且在反射型衍射光栅之间具有在源电极和漏电极之间的弯曲电子路径。 电子的量子衍射效应用于衍射漏极电流的控制。

公开(公告)号：US5883419A

公开(公告)日：1999-03-16

申请号：US850013

申请日：1997-05-01

Applicant: Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

Inventor： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC: H01L41/00 ,  H01L45/00 ,  B02J17/40 ,  B05D3/06

CPC classification number: H01L45/00

Abstract: A transistor in accordance with the invention comprises an ultra-thin Mo--C film functioning as a channel for an electron flow with two ends of the thin metal film functioning as source and drain terminals of the transistor, respectively; a piezoelectric film formed on the Mo--C film, for producing a force in accordance with an applied electric field provided by a gate voltage; and an electrode film formed on the piezoelectric film functioning as a gate of the transistor to which the gate voltage is applied to produce the applied electric field; and wherein a resistance of the Mo--C film between the source and drain terminals changes in accordance with the force produced in response to the applied gate voltage. This transistor can be used as an element of the three dimensional integrated circuit with a laminated structure.

Abstract translation: 根据本发明的晶体管包括用作电子流的通道的超薄Mo-C膜，其中薄金属膜的两端分别用作晶体管的源极和漏极端子; 形成在Mo-C膜上的压电膜，用于根据由栅极电压提供的施加的电场产生力; 以及形成在作为施加栅极电压的晶体管的栅极的压电膜上产生施加的电场的电极膜; 并且其中源极和漏极端子之间的Mo-C膜的电阻根据施加的栅极电压产生的力而改变。 该晶体管可以用作具有层叠结构的三维集成电路的元件。

公开(公告)号：US5760675A

公开(公告)日：1998-06-02

申请号：US716550

申请日：1996-09-19

Applicant: Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

Inventor： Seong-Jae Lee ,  Kyoung-Wan Park ,  Min-Cheol Shin

IPC: G01L1/18 ,  G01L1/22 ,  H01L29/84 ,  H01L41/00

CPC classification number: G01L1/2293

Abstract: Disclosed is the method of producing a piezo-device utilizing an ultra-thin Mo-C film as a piezoresistive material for a general class of improved piezo-device with the high sensitivity and the weak temperature dependence.

Abstract translation: 公开了利用超薄Mo-C膜作为压敏电阻材料的压电器件的制造方法，该压电器件具有高灵敏度和弱温度依赖性的一类改进的压电器件。