公开(公告)号：US20110081210A1

公开(公告)日：2011-04-07

申请号：US12994608

申请日：2009-09-28

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: B23C5/20 ,  B23C5/06 ,  B23B27/16

CPC classification number: B23C5/207 ,  B23C2200/128 ,  B23C2200/205 ,  Y10T407/1924 ,  Y10T407/23 ,  Y10T409/303752

Abstract: A cutting insert is provided with an upper surface, a lower surface, side surfaces for interconnecting the upper surface and the lower surface, cutting edges located at the intersections between the upper surface and the side surfaces, and grooves located in the side surfaces, extending from the upper surface toward the lower surface, and dividing the cutting edges. Each of the grooves is provided with a first edge and a second edge which are located at the edges of the groove in the width direction thereof and extending from the upper surface toward the lower surface. In a side view, the first edge has a first separated section located on the upper surface side and, as the first edge extends toward the lower surface, separated away from a reference line which passes through the midpoint of the groove in the width direction thereof and is substantially perpendicular to the lower surface. Also, in the side view, the second edge has a second separated section located on the upper surface side and separated away from the reference line as the second edge extends toward the lower surface.

Abstract translation: 切削刀片设置有上表面，下表面，用于互连上表面和下表面的侧表面，位于上表面和侧表面之间的交叉处的切削刃和位于侧表面中的凹槽，延伸 从上表面向下表面分割切削刃。 每个凹槽设置有第一边缘和第二边缘，该第一边缘和第二边缘位于沿其宽度方向的槽的边缘并且从上表面朝向下表面延伸。 在侧视图中，第一边缘具有位于上表面侧的第一分离部分，并且当第一边缘朝向下表面延伸时，远离通过槽的宽度方向的中点的参考线分离 并且基本上垂直于下表面。 此外，在侧视图中，第二边缘具有位于上表面侧上的第二分离部分，并且随着第二边缘朝向下表面延伸而与基准线分离。

公开(公告)号：US20090188356A1

公开(公告)日：2009-07-30

申请号：US12091906

申请日：2006-10-24

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: B26D3/00 ,  B26D1/12

CPC classification number: B23C5/109 ,  B23C5/06 ,  B23C5/205 ,  B23C5/207 ,  B23C2200/081 ,  B23C2200/087 ,  B23C2200/128 ,  B23C2200/205 ,  B23C2200/323 ,  Y10T83/0591 ,  Y10T407/1912 ,  Y10T407/22 ,  Y10T407/23 ,  Y10T407/235

Abstract: An object of the invention is to provide a cutting insert suitably usable even in a cutting. A cutting insert of the invention is formed in a substantially plate shape, wherein a groove part (6) is formed in a flank face (4), a main cutting edge (5) is composed of a plurality of main cutting edge divisions (5a) divided by the groove part (6), and a concave part (7) depressed in a rake face (2) is formed in a vicinity corresponding to each of the main cutting edge divisions (5) in the rake face (2).

Abstract translation: 本发明的目的是提供即使在切割中也可适当使用的切削刀片。 本发明的切削刀片形成为大致板状，其中在侧面（4）上形成有槽部（6），主切削刃（5）由多个主切削刃（5a） ），并且在前刀面（2）中凹入的凹部（7）形成在与前刀面（2）中的每个主切削刃分割部（5）对应的附近。

公开(公告)号：US20080260476A1

公开(公告)日：2008-10-23

申请号：US11576337

申请日：2005-09-29

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: B23C5/20 ,  B26D1/12

CPC classification number: B23C5/06 ,  B23C5/202 ,  B23C2200/085 ,  B23C2200/125 ,  B23C2200/128 ,  B23C2200/205 ,  B23C2200/323 ,  B23C2210/0442 ,  B23C2210/325 ,  B23C2210/66 ,  Y10T407/1906 ,  Y10T407/191 ,  Y10T407/22 ,  Y10T407/23 ,  Y10T407/235

Abstract: A throwaway insert enabling the use of a holder for a long period and having excellent chip evacuation is provided. The throwaway insert is formed in a substantially polygonal plate shape and includes a rake face formed on an upper surface thereof a relief face formed on a side surface thereof a main cutting edge formed along a ridge representing an intersection of the rake face and the relief face, which is divided into a plurality of main cutting edge divisions by at least one groove formed on the relief face, and a projection formed so as to protrude from the rake face in correspondence with each of the main cutting edge divisions.

Abstract translation: 提供了能够长期使用保持器并且具有优异的排屑的一次性插入件。 一次性插入件形成为大致多边形的板状，并且包括在其上表面上形成有在其侧表面上形成的浮雕面的前刀面，该主切削刃沿着表示前刀面和浮雕面的交叉的脊 ，其通过形成在所述浮雕面上的至少一个槽分割成多个主切削刃分割部，并且与所述主切削刃部分对应地形成为从所述前刀面突出。

公开(公告)号：US20080022144A1

公开(公告)日：2008-01-24

申请号：US11812624

申请日：2007-06-20

Applicant: Yukinari Shibata ,  Nobuyuki Saito ,  Tomonaga Hasegawa ,  Takuya Ishida

Inventor： Yukinari Shibata ,  Nobuyuki Saito ,  Tomonaga Hasegawa ,  Takuya Ishida

IPC: G06F1/04

CPC classification number: G06F1/3203 ,  H04L25/0272

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract translation: 数据传送控制装置包括：通过驱动串行信号线发送OUT数据的OUT传送发送器电路;通过驱动串行信号线发送时钟信号CLK的时钟传送发送器电路;产生时钟信号的PLL电路 CLK，以及设置掉电模式的掉电设置电路。 在第一掉电模式中，OUT传输发射机电路被设置为掉电模式，并且时钟传送发射机电路被设置为掉电模式以停止目标侧数据的系统时钟信号 传输控制装置。 在第二个掉电模式下，OUT传输发射机电路设置为掉电模式，而不将时钟传输发射机电路设置为掉电模式。

公开(公告)号：US20070156932A1

公开(公告)日：2007-07-05

申请号：US11604011

申请日：2006-11-22

Applicant: Shoichiro Kasahara ,  Fumikazu Komatsu ,  Mitsuaki Sawada ,  Yoshiyuki Kamihara ,  Takuya Ishida

Inventor： Shoichiro Kasahara ,  Fumikazu Komatsu ,  Mitsuaki Sawada ,  Yoshiyuki Kamihara ,  Takuya Ishida

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: An integrated circuit device includes a common transceiver macrocell including a circuit necessary for host operation and a circuit necessary for device operation. The common transceiver macrocell includes an analog front-end circuit and a high-speed logic circuit. The high-speed logic circuit includes a parallel/serial conversion circuit, a first parallel interface which serves as an interface between an external circuit and the parallel/serial conversion circuit, a sampling clock generation circuit, a serial/parallel conversion circuit, and a second parallel interface which serves as an interface between the serial/parallel conversion circuit and the external circuit.

Abstract translation: 集成电路装置包括包括主机操作所必需的电路和设备操作所需的电路的公共收发器宏单元。 公共收发器宏单元包括模拟前端电路和高速逻辑电路。 高速逻辑电路包括并行/串行转换电路，用作外部电路和并行/串行转换电路之间的接口的第一并行接口，采样时钟产生电路，串行/并行转换电路和 第二并行接口，用作串行/并行转换电路和外部电路之间的接口。

公开(公告)号：US07234901B2

公开(公告)日：2007-06-26

申请号：US10659933

申请日：2003-09-11

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: B23B27/16

CPC classification number: B23B27/141 ,  B23B2200/0428 ,  B23B2200/0476 ,  B23B2200/049 ,  B23B2200/323 ,  Y10T83/9319 ,  Y10T407/23 ,  Y10T407/235 ,  Y10T407/24

Abstract: A throw-away tip of which two principal surfaces each has a land surface provided along the periphery thereof, a central surface provided on the inside of the land surface, a recess (a chip breaker groove) interposed therebetween, and at least one protrusion that extends from the central surface toward the land surface, wherein height of the land surface is made equal to the height of at least the top surface of the protrusion so that at least the top surface of the protrusion of the central surface and the land surface both serve as contact surface is provided.

Abstract translation: 一个丢弃尖端，其两个主表面各自具有沿着其周边设置的台面，设置在台面的内侧上的中心表面，插入其间的凹部（断屑槽）和至少一个突出部， 从中心表面向陆面延伸，其中使得台面的高度至少等于突起的顶表面的高度，使得至少中心表面的凸起的顶表面和台面两者均为 用作接触面。

公开(公告)号：US20060250091A1

公开(公告)日：2006-11-09

申请号：US11270321

申请日：2005-11-09

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: H05B37/00

CPC classification number: H05B33/0818 ,  H05B33/0809

Abstract: A positive power voltage is supplied to a power line. When a high signal is applied to an input terminal, a transistor, which is a switching element, becomes the ON state, and a current flow only to a light-emitting diode, and thus only the light-emitting diode is lighted. When a low signal is applied to the input terminal, the transistor becomes the OFF state, and current flows to the light-emitting diodes. Since the values of the resistors are determined so that the current flowing to the light-emitting diode becomes sufficiently low, only the light-emitting diode is lighted. The light-emitting-diodes are serially connected in order not to receive an affect of the characteristics of the transistor.

Abstract translation: 正电源电压被提供给电力线。 当高信号被施加到输入端子时，作为开关元件的晶体管变为导通状态，并且电流仅流向发光二极管，因此仅发光二极管点亮。 当低信号被施加到输入端子时，晶体管变为截止状态，电流流向发光二极管。 由于电阻值被确定为使得流到发光二极管的电流变得足够低，所以仅发光二极管点亮。 发光二极管串联连接，以免受到晶体管特性的影响。

公开(公告)号：US20050105549A1

公开(公告)日：2005-05-19

申请号：US11017858

申请日：2004-12-22

Applicant: Takuya Ishida ,  Yoshiyuki Kamihara

Inventor： Takuya Ishida ,  Yoshiyuki Kamihara

IPC: G06F13/38 ,  H04L12/28 ,  H04L12/40 ,  H04L12/64 ,  H04L13/08 ,  H04L29/08 ,  H04L12/66 ,  H04J3/22

CPC classification number: H04L12/40052 ,  H04L12/2801 ,  H04L12/40071 ,  H04L49/90 ,  H04L49/9042 ,  H04L69/32

Abstract: An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label tl of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within tl, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.

Abstract translation: 本发明的目的是提供一种数据传输控制装置和电子设备，其可以减少固件中的处理开销并实现高速数据传输。 在根据IEEE 1394标准的数据传输控制装置中，分组的报头被写入报头区域，分组的ORB（SBP-2的数据）被写入ORB区域，并且流（数据 分组的应用层）被写入流区域。 流区域由硬件根据完整和空白信号进行管理。 指示信息被包含在请求分组的交易标签t1内，并且当接收到响应分组时，响应分组的报头，ORB和流被写入由包括在t1内的指示信息指示的区域。 该设备还具有寄存器TSR和TER，其包含用于保护流区域中的传输区域的地址TS和TE，并且寄存包含地址RS和RE的RSR和RER，用于确保其中的接收区域。

公开(公告)号：US06857028B1

公开(公告)日：2005-02-15

申请号：US09787218

申请日：2000-07-12

Applicant: Takuya Ishida ,  Yoshiyuki Kamihara

Inventor： Takuya Ishida ,  Yoshiyuki Kamihara

IPC: G06F13/38 ,  H04L12/28 ,  H04L12/40 ,  H04L12/64 ,  H04L13/08 ,  H04L29/08 ,  G06F3/00 ,  G06F13/00 ,  G06F13/42 ,  G06F15/16

CPC classification number: H04L12/40052 ,  H04L12/2801 ,  H04L12/40071 ,  H04L49/90 ,  H04L49/9042 ,  H04L69/32

Abstract: An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label t1 of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within t1, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.

Abstract translation: 本发明的目的是提供一种数据传输控制装置和电子设备，其可以减少固件中的处理开销并实现高速数据传输。 在根据IEEE 1394标准的数据传输控制装置中，分组的报头被写入报头区域，分组的ORB（SBP-2的数据）被写入ORB区域，并且流（数据 分组的应用层）被写入流区域。 流区域由硬件根据完整和空白信号进行管理。 指示信息包含在请求分组的事务标签t1内，并且响应分组的报头，ORB和流被写入到包含在t1内的指示信息所指示的区域中。 该设备还具有寄存器TSR和TER，其包含用于保护流区域中的传输区域的地址TS和TE，并且寄存包含地址RS和RE的RSR和RER，用于确保其中的接收区域。

公开(公告)号：US06732204B2

公开(公告)日：2004-05-04

申请号：US09805029

申请日：2001-03-14

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: G06F1312

CPC classification number: G06F13/4059

Abstract: The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a stage before a parallel-serial conversion circuit on the transmission side and an NRZI decoder and a bit unstuffing circuit are provided in a stage after a serial-parallel conversion circuit on the reception side, so that bit stuffing, NRZI encoding, NRZI decoding, and bit unstuffing are implemented on parallel data, not serial data. Any bits that have overflowed due to the bit insertion are carried forward to data for the next clock cycle and any deficiency of bits caused by bit deletion is moved up from the data of the next clock cycle. Insertion (or deletion) of bits is based on the thus calculated bit stuffing (or bit unstuffing) position and the range of parallel data to be output is based on the accumulated total of the number of bits that overflow (or contract).

Abstract translation: 目的是提供一种以慢时钟频率实现位插入，编码，解码和位删除的数据传输控制设备和电子设备。 在发送侧的并行 - 串行转换电路之前的一个阶段提供位填充电路和NRZI编码器，并且在接收侧的串行 - 并行转换电路之后的级中提供NRZI解码器和位不充电电路，因此 该位填充，NRZI编码，NRZI解码和位解混合在并行数据而不是串行数据上实现。 由于位插入而溢出的任何位被转发到下一个时钟周期的数据，并且由位删除引起的位的任何不足都从下一个时钟周期的数据向上移动。 位的插入（或删除）基于这样计算的位填充（或位不填充）位置，并且要输出的并行数据的范围基于累积（或收缩）的位数的累积总数。