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公开(公告)号：KR1020000056006A
公开(公告)日：2000-09-15
申请号：KR1019990004987
申请日：1999-02-12
Applicant: 삼성전자주식회사
IPC: H01L21/334
Abstract: PURPOSE: A method for manufacturing a gate spacer of a semiconductor device is provided to shorten a whole processing time by an improved uniformity of a layer thickness and a rapid growth of an evaporated layer, and to decrease a stress given to a source/drain region of a transistor by an evaporation under a low temperature atmosphere. CONSTITUTION: A method for manufacturing a gate spacer of a semiconductor device comprises the steps of: inducing a tetraethoxysilane(TEOS) layer to a high temperature chamber in which a plurality of semiconductor substrates having a gate pattern are loaded; forming a silicon oxidation layer on the semiconductor substrate; and etching back the silicon oxidation layer to form a gate spacer on a side wall of the gate pattern.
Abstract translation: 目的：提供一种用于制造半导体器件的栅极间隔物的方法，通过改善层厚度的均匀性和蒸发层的快速生长来缩短整个处理时间，并且减小施加到源极/漏极区域 的晶体管通过在低温气氛下的蒸发。 构成：用于制造半导体器件的栅极间隔物的方法包括以下步骤：向其中加载具有栅极图案的多个半导体衬底的高温室诱导四乙氧基硅烷（TEOS）层; 在半导体衬底上形成硅氧化层; 并且蚀刻硅氧化层以在栅极图案的侧壁上形成栅极间隔物。
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