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Patent Agency Ranking
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公开(公告)号：KR1019890004319B1
公开(公告)日：1989-10-30
申请号：KR1019870002595
申请日：1987-03-21
Applicant: 삼성전자주식회사
Inventor： 변형구
IPC: H03M9/00
Abstract: The circuit includes multiplexers (MUT1MUT8) for selecting and for multiplexing input data according to input selection signal (S/P), D- type flip-flops (FF1-FF8) for shifting output signals of multiplexers utilizing clock pulse, a latch unit (LAT) for latching data from flip-flops utilizing latch clock pulse (CLK), and buffers (B0-B8) for prohibiting collision of data from input terminals during conversion of serial or parallel data.
Abstract translation: 电路包括用于根据输入选择信号（S / P）选择和复用输入数据的多路复用器（MUT1MUT8），用于利用时钟脉冲移位复用器的输出信号的D-型触发器（FF1-FF8），锁存单元 LAT），用于使用锁存时钟脉冲（CLK）来锁存来自触发器的数据，以及缓冲器（B0-B8），用于在串行或并行数据转换期间禁止来自输入端的数据的冲突。
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公开(公告)号：KR1019890004184B1
公开(公告)日：1989-10-23
申请号：KR1019860010217
申请日：1986-12-01
Applicant: 삼성전자주식회사
Inventor： 변형구
IPC: H03M13/00
Abstract: The method is for simplifying the error correction process and reducing the memory capacity required for information storage by processing the information resulted from the decoding of the transmitted information with one bit per a code word. A receiving decoder (60) attaches a flag to the code word according to the error correction result to find out the error position so that the number of required memory can be reduced.
Abstract translation: 该方法用于简化纠错处理，并且通过处理由每个码字一位对所发送的信息进行解码而产生的信息来减少信息存储所需的存储容量。 接收解码器（60）根据纠错结果将标志附加到码字，以找出错误位置，从而可以减少所需存储器的数量。
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