公开(公告)号：KR1020140147367A

公开(公告)日：2014-12-30

申请号：KR1020130070471

申请日：2013-06-19

Applicant: 삼성전자주식회사

Inventor： 김용준 ,  이길호 ,  김기준 ,  손명수

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76807

Abstract: Provided is a manufacturing method of a semiconductor device which forms; a mold layer on a substrate; a first damascene mask layer and a first mask layer on the mold layer; a first mask layer pattern by etching the first mask layer; a first damascene pattern by etching the first damascene mask layer partially by using the first mask layer pattern; a second damascene mask layer on the first mask layer pattern to bury the first damascene pattern; and a second damascene pattern which is overlapped with the first damascene pattern partially by etching the second damascene mask layer and the first mask layer pattern. The manufacturing method of the semiconductor device connects the first damascene pattern and the second damascene pattern by eliminating a portion of the first mask pattern which is exposed by the second damascene pattern and forms a third damascene pattern on the second damascene mask layer to bury the second damascene pattern and forms a trench extended from the first and second damascene patterns by etching the third, second, and first damascene mask layers, and the mold layer by using the residual first mask layer pattern.

Abstract translation: 提供一种形成半导体器件的制造方法; 基底上的模具层; 模具层上的第一镶嵌掩模层和第一掩模层; 通过蚀刻第一掩模层的第一掩模层图案; 通过使用第一掩模层图案部分地蚀刻第一镶嵌掩模层的第一镶嵌图案; 在第一掩模层图案上的第二镶嵌掩模层以埋藏第一镶嵌图案; 以及通过蚀刻第二镶嵌掩模层和第一掩模层图案部分地与第一镶嵌图案重叠的第二镶嵌图案。 半导体器件的制造方法通过消除由第二镶嵌图案暴露的第一掩模图案的一部分并在第二镶嵌掩模层上形成第三镶嵌图案来连接第一镶嵌图案和第二镶嵌图案，以将第二镶嵌图案 通过使用残留的第一掩模层图案蚀刻第三，第二和第一镶嵌掩模层和模具层，形成从第一和第二镶嵌图案延伸的沟槽。

公开(公告)号：KR1020140019563A

公开(公告)日：2014-02-17

申请号：KR1020120085784

申请日：2012-08-06

Applicant: 삼성전자주식회사

Inventor： 이길호 ,  김기준 ,  박세웅

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/76224 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76832 ,  H01L27/228 ,  H01L43/08 ,  H01L21/76205

Abstract: Provided is a non-volatile memory device providing method, capable of securing a short margin with gate patterns arranged in the lower part of a bit line at the same time as increasing the thickness of bit lines at a peripheral region. The method for manufacturing the non-volatile memory device comprises the steps of: forming a transistor in a first region on a substrate; forming a contact connected with the transistor; forming a memory cell arranged two-dimensionally in a second region on the substrate; sequentially forming the contact, a stopping film to cover a data storage unit, and an interlayer insulating film; forming a first trench which exposes the stopping film on the contact, wherein the lower part of the first trench is formed to be lower than the lower part of the data storage unit; and forming a second trench which exposes the contact by penetrating the stopping film.

Abstract translation: 提供了一种非易失性存储器件提供方法，其能够在与周边区域中增加位线的厚度同时同时确保布置在位线下部的栅极图案的短边。 用于制造非易失性存储器件的方法包括以下步骤：在衬底上的第一区域中形成晶体管; 形成与晶体管连接的触点; 形成在所述基板上的第二区域中二维布置的存储单元; 顺序地形成接触，覆盖数据存储单元的停止膜和层间绝缘膜; 形成将所述停止膜暴露在所述触点上的第一沟槽，其中所述第一沟槽的下部形成为低于所述数据存储单元的下部; 以及形成通过穿透止动膜使接触部暴露的第二沟槽。

公开(公告)号：KR101291222B1

公开(公告)日：2013-07-31

申请号：KR1020070122737

申请日：2007-11-29

Applicant: 삼성전자주식회사

Inventor： 김철규 ,  강윤호 ,  김기준

IPC: G11C13/02

CPC classification number: G11C11/5678 ,  G11C13/0004

Abstract: 상변화 메모리 소자의 동작 방법에 관해 개시되어 있다. 본 발명의 동작 방법은 상변화층 및 상기 상변화층에 전압을 인가하는 수단을 포함하는 상변화 메모리 소자의 동작 방법에 있어서, 상기 상변화층에 리세트 전압을 인가하되, 상기 리세트 전압은 연속 인가되는 적어도 두 개의 펄스 전압을 포함하는 상변화 메모리 소자의 동작 방법을 제공한다.

公开(公告)号：KR100858083B1

公开(公告)日：2008-09-10

申请号：KR1020060101570

申请日：2006-10-18

Applicant: 삼성전자주식회사

Inventor： 강윤호 ,  김기준 ,  서동석

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: 하부전극 콘택층과 상변화층 사이에 넓은 접촉면적을 갖는 상변화 메모리 소자 및 그 제조 방법에 관해 개시되어 있다. 여기서 본 발명은 비어홀을 채운 하부전극 콘택층, 상변화층 및 상부 전극층을 포함하는 스토리지 노드와 상기 하부전극 콘택층에 연결되는 스위칭 소자를 포함하는 상변화 메모리 소자에 있어서, 상기 하부전극 콘택층는 상기 상변화층으로 돌출된 돌출부를 갖는 특징으로 하는 상변화 메모리 소자 및 그 제조 방법을 제공한다. 상기 돌출부는 하부전극 콘택층의 식각률이 낮은 식각조건으로 그 둘레의 층간 절연층을 건식이나 습식식각하여 형성할 수 있고, 선택적 성장법으로 형성할 수 있으며, 증착 및 사진식각공정을 이용하여 형성할 수도 있다. 상기 선택적 성장법이나 증착 및 사진식각공정 이후에 상기 건식이나 습식식각을 더 실시할 수 있다.

公开(公告)号：KR1020080028704A

公开(公告)日：2008-04-01

申请号：KR1020060094343

申请日：2006-09-27

Applicant: 삼성전자주식회사

Inventor： 서동석 ,  김상열 ,  김기준 ,  강윤호 ,  노진서

IPC: H01L27/115 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: An apparatus for analyzing a phase change material and a method for analyzing a phase change material using the same are provided to minimize power consumption of a PRAM by optimizing a PRAM programming process. An apparatus for analyzing a phase change material includes a holder(225) for holding a sample(200) including an analyzing sample, a light source unit for irradiating the light onto the sample, a first member for analyzing the light reflected from the sample, and a second member for converting an analyzed result to a digital signal. The apparatus for analyzing a phase change material further includes an electrical pulse applying unit and an interworking unit. The electrical pulse applying unit applies an electrical pulse to the sample during the light is irradiated onto the sample. The interworking unit operates the electrical pulse applying unit and a member for converting the analyzed result to a digital signal.

Abstract translation: 提供一种用于分析相变材料的装置和使用其的相变材料的分析方法，以通过优化PRAM编程过程来最小化PRAM的功耗。 用于分析相变材料的装置包括用于保持包括分析样品的样品（200）的保持器（225），用于将光照射到样品上的光源单元，用于分析从样品反射的光的第一构件， 以及用于将分析结果转换为数字信号的第二成员。 用于分析相变材料的装置还包括电脉冲施加单元和互配单元。 电脉冲施加单元在光照射到样品上时向样品施加电脉冲。 互通单元操作电脉冲施加单元和用于将分析结果转换为数字信号的构件。

公开(公告)号：KR100610027B1

公开(公告)日：2006-08-09

申请号：KR1020000000593

申请日：2000-01-07

Applicant: 삼성전자주식회사

Inventor： 송병철 ,  김기준 ,  임훈 ,  윤종밀

IPC: G11C7/12

Abstract: 본 발명은 반도체 메모리에 관한 것으로, 특히 반도체 메모리에서 비트라인 신호쌍의 디벨럽 마진(Develop Margin)을 충분히 확보함으로써 궁극적으로 칩 디바이스의 성능을 향상시키는 반도체 메모리에 있어서 비트라인 신호쌍의 디벨럽 마진 개선장치에 관한 것이다.
메모리, 비트라인, 디벨럽 마진, 프리차지

公开(公告)号：KR1020020071163A

公开(公告)日：2002-09-12

申请号：KR1020010011135

申请日：2001-03-05

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: G11C29/00

Abstract: PURPOSE: An apparatus for testing a serial chip is provided to reduce efficiently a time for test by using a data transfer circuit for transferring serial test data bits and parallel test data bits, simultaneously. CONSTITUTION: A circuit under test(20) has a plurality of function cells. A serial input terminal(50) is used for receiving serial test data. A parallel data input terminal(60) is used for receiving parallel test data. The first data latch circuit(30) latches parallel test data bits during a predetermined time in response to a predetermined control signal(ICON). The second data latch circuit(40) latches serial test data bits during a predetermined time in response to a predetermined control signal(SCON). A data transfer circuit(10) transfers the serial test data bits to the circuit under test(20) and the parallel test data bits to the circuit under test(20), simultaneously.

Abstract translation: 目的：提供一种用于测试串行芯片的设备，用于同时通过使用用于传送串行测试数据位和并行测试数据位的数据传输电路有效减少测试时间。 构成：被测电路（20）具有多个功能单元。 串行输入端子（50）用于接收串行测试数据。 并行数据输入端子（60）用于接收并行测试数据。 响应于预定的控制信号（ICON），第一数据锁存电路（30）在预定时间内锁存并行测试数据位。 第二数据锁存电路（40）响应于预定的控制信号（SCON）在预定时间期间锁存串行测试数据位。 数据传输电路（10）同时将串行测试数据位传送到被测电路（20）和并行测试数据位给被测电路（20）。

公开(公告)号：KR1020010019178A

公开(公告)日：2001-03-15

申请号：KR1019990035460

申请日：1999-08-25

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: G01R19/165

Abstract: PURPOSE: A device of testing voltage level having a simple circuit structure is provided to test voltage level inside the semiconductor IC(Integrated Circuit) chip. CONSTITUTION: In a device testing the operation voltage(Vlcd) of a semiconductor IC(Integrated Circuit) chip driving an LCD panel, the first reference voltage generator(12) generates the first reference voltage(V1) corresponding to the maximum of the operation voltage(Vlcd). The first comparator(14) compares between the operation voltage(Vlcd) and the first reference voltage(V1). The second reference voltage generator(22) generates the second reference voltage(V2) corresponding to the minimum of the operation voltage(Vlcd). The second comparator(24) compares between the operation voltage(Vlcd) and the second reference voltage(V2)

Abstract translation: 目的：提供具有简单电路结构的测试电压电平的装置，以测试半导体IC（集成电路）芯片内部的电压电平。 构成：在测试驱动LCD面板的半导体IC（集成电路）芯片的工作电压（Vlcd）的装置中，第一参考电压发生器（12）产生对应于操作电压的最大值的第一参考电压（V1） （VLCD）。 第一比较器（14）在操作电压（V1cd）和第一参考电压（V1）之间进行比较。 第二参考电压发生器（22）产生对应于操作电压（Vlcd）的最小值的第二参考电压（V2）。 第二比较器（24）将工作电压（V1cd）和第二参考电压（V2）

公开(公告)号：KR1020010001025A

公开(公告)日：2001-01-05

申请号：KR1019990019985

申请日：1999-06-01

Applicant: 삼성전자주식회사

Inventor： 김기준

IPC: H01L21/027

CPC classification number: H01L21/31144 ,  G03F1/70

Abstract: PURPOSE: A method for manufacturing a fine pattern of a semiconductor device is to provide an optimized profile, by patterning a material layer using at least two sub-photomasks having patterns different from each other. CONSTITUTION: A material layer to pattern is formed on a semiconductor substrate. An etching mask layer is formed on the material layer. The etching mask layer is patterned more than twice by independently using at least two sub-photomasks. A material pattern having a plurality of patterns is formed on the semiconductor substrate by patterning the material layer using the twice-etched etching mask as an etching mask.

Abstract translation: 目的：制造半导体器件的精细图案的方法是通过使用具有彼此不同的图案的至少两个子光掩模图案化材料层来提供优化的外形。 构成：在半导体衬底上形成图形材料层。 在材料层上形成蚀刻掩模层。 通过使用至少两个子光掩模独立地将蚀刻掩模层图案化两次以上。 通过使用两次蚀刻的蚀刻掩模作为蚀刻掩模对材料层进行图案化，在半导体衬底上形成具有多个图案的材料图案。

公开(公告)号：KR100258347B1

公开(公告)日：2000-06-01

申请号：KR1019980001526

申请日：1998-01-20

Applicant: 삼성전자주식회사

Inventor： 김기준 ,  윤종밀 ,  김성봉

IPC: H01L21/24

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/11

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to reduce the junction leakage of a conductive layer which is used as an active layer by performing a heat treatment process after coating a refractory metal layer. CONSTITUTION: The first transistor is formed in an active area of a semiconductor substrate(100) and the second transistor is formed adjacent to the first transistor. An active area of the first transistor is connected to a gate of the second transistor by a conductive material. An insulating layer(114) is formed on an upper surface of the semiconductor substrate(100). Then, the insulating layer(114) formed one of a source area (110) or a drain area(112) of the first transistor and on an upper portion of the gate(106) of the second transistor are removed. After coating silicon for forming silicide on the resulted structure, a photoresist film(120) is formed on the connection region between the first and second transistors. After removing the photoresist film(120), a metal layer is formed on the entire surface of the structure. A silicide layer is formed on the connection region by performing a heat-treating process.

Abstract translation: 目的：提供一种制造半导体器件的方法，以通过在涂覆难熔金属层之后进行热处理工艺来减少用作有源层的导电层的结漏电。 构成：第一晶体管形成在半导体衬底（100）的有源区中，并且第二晶体管形成为与第一晶体管相邻。 第一晶体管的有源区通过导电材料连接到第二晶体管的栅极。 绝缘层（114）形成在半导体衬底（100）的上表面上。 然后，去除形成第一晶体管的源极区域（110）或漏极区域（112）中以及在第二晶体管的栅极（106）的上部上的绝缘层（114）。 在所得到的结构上涂覆用于形成硅化物的硅之后，在第一和第二晶体管之间的连接区域上形成光致抗蚀剂膜（120）。 在去除光致抗蚀剂膜（120）之后，在结构的整个表面上形成金属层。 通过进行热处理工艺在连接区域上形成硅化物层。