公开(公告)号：JP2011193505A

公开(公告)日：2011-09-29

申请号：JP2011100172

申请日：2011-04-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： WONG WILSON ,  CHAN DORIS PO CHING ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  HOANG TIM TRI ,  LAI TIN H ,  TRAN THUNGOC M

IPC: H04L25/03 ,  H04B3/06

CPC classification number: H04L25/03885

Abstract: PROBLEM TO BE SOLVED: To provide a digital adaptation circuit network and a method for a programmable logic device.
SOLUTION: The method controls the equalization of an incoming data signal. The method includes steps for: detecting bits having two consecutive different values out of the data signal; determining whether transition in the incoming data signal between the two bits is relatively low in speed or relatively high in speed; and increasing the equalization of the incoming data signal when the transition is relatively low in speed.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供数字适配电路网络和可编程逻辑器件的方法。

解决方案：该方法控制输入数据信号的均衡。 该方法包括以下步骤：从数据信号中检测具有两个连续不同值的位; 确定两个比特之间的输入数据信号中的转换是相对低的速度还是相对较高的速度; 并且当转换速度相对较低时，增加输入数据信号的均衡。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007282183A

公开(公告)日：2007-10-25

申请号：JP2006351009

申请日：2006-12-27

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： SHUMARAYEV SERGEY ,  BEREZA BILL W ,  LEE CHONG H ,  RAKESH PATEL H ,  WONG WILSON

IPC: H03K19/173

CPC classification number: H04L5/14 ,  H03K19/17744 ,  H04L27/00

Abstract: PROBLEM TO BE SOLVED: To provide a programmable logic device ("PLD") that can support over a wide range of assumed serial data communication speeds (including 10 to 12 Gbps).
SOLUTION: A high-speed serial data transceiver network on a programmable logic device ("PLD") includes some channels that are able to operate at data rates, up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates, up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase-locked loop ("PLL") network, and have other circuit components that are typically needed for handling the data that are transmitted at relatively low data rates. The relatively high-speed channels are served by a relatively high-speed PLL network, and have other circuit components that are typically needed for handling data that are transmitted at relatively high data rates.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可支持广泛范围的假设串行数据通信速度（包括10到12 Gbps）的可编程逻辑器件（“PLD”）。 解决方案：可编程逻辑器件（“PLD”）上的高速串行数据收发器网络包括一些能够以数据速率操作的通道，最多可达到第一个相对较低的最大数据速率，以及其他通道 能够以高达第二，相对较高的最大数据速率的数据速率进行操作。 相对低速的通道由相对低速的锁相环（“PLL”）网络服务，并且具有处理以相对低的数据速率传输的数据通常需要的其他电路部件。 相对高速的信道由相对高速的PLL网络服务，并且具有通常用于处理以相对高的数据速率发送的数据所需的其他电路部件。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007043717A

公开(公告)日：2007-02-15

申请号：JP2006211486

申请日：2006-08-02

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： HOANG TIM T ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  RAKESH PATEL H

IPC: H03L7/08 ,  H03K5/00 ,  H04L7/033

CPC classification number: H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a CDR architecture operable over a wide range of data rates. SOLUTION: A wide range and dynamically reconfigurable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammable without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可在宽范围的数据速率下操作的CDR架构。 解决方案：宽范围和动态可重配置的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 这些参数可以动态重新编程，而不会关闭电路或PLD。 这允许CDR电路在各种标准和协议之间进行即时切换。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007028619A

公开(公告)日：2007-02-01

申请号：JP2006192210

申请日：2006-07-12

Applicant: Altera Corp ,  アルテラ コーポレイションAltera Corporation

Inventor： ASADUZZAMAN KAZI ,  SHUMARAYEV SERGEY Y ,  TRAN THUNGOC M ,  WONG WILSON ,  PATEL RAKESH

IPC: H03K19/0175 ,  H03K5/12 ,  H03K17/687

CPC classification number: H03K17/164

Abstract: PROBLEM TO BE SOLVED: To variably control a slew rate in a transmitter to be used for data transfer employing variable slew rate or various transmission protocols.
SOLUTION: A transmitter driver circuit having a variable slew rate provided by the present invention comprises a pre-driver circuit for generating a driver input signal with a variable slew rate and a driver circuit for receiving a slew rate controlled signal from the pre-driver circuit. The pre-driver circuit comprises a plurality of pre-driver stages each selectively operable to drive a pre-driver output signal related to a signal received at an input and a control circuit which responds to at least one slew rate control signal, the control circuit operates to selectively enable the pre-driver stages and to change a pre-driver output signal slew rate, and the driver circuit generates a driver output signal with a slew rate related to a slew rate of the pre-driver output signal.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：可变地控制用于使用可变转换速率或各种传输协议的数据传输的发射机中的压摆率。 解决方案：由本发明提供的具有可变转换速率的发射器驱动电路包括用于产生具有可变转换速率的驱动器输入信号的预驱动器电路和用于从预先接收压摆率控制信号的驱动电路 驱动电路。 预驱动器电路包括多个预驱动器级，每个预驱动器级可选择性地操作以驱动与在输入处接收到的信号相关的预驱动器输出信号和响应于至少一个压摆率控制信号的控制电路，控制电路 操作以选择性地启用预驱动器级并改变预驱动器输出信号转换速率，并且驱动器电路产生具有与预驱动器输出信号的转换速率相关的转换速率的驱动器输出信号。 版权所有（C）2007，JPO＆INPIT