公开(公告)号：WO1996017255A2

公开(公告)日：1996-06-06

申请号：PCT/US1995015285

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  ZHAO, Yang ,  LEWIS, Stephen

IPC: G01P15/125

CPC classification number: G01P15/131 ,  G01P15/125 ,  G01P2015/0814

Abstract: A circuit for minimizing electrostatic forces in capacitance-based sensor circuits. A sensor includes a movable mass (10) that forms the center electrode of two differential capacitors, a sensing differential capacitor (24) and an actuator differential capacitor (52). The other two electrodes (18, 20, 46, 48) of each differential capacitor are fixed. Oppositely phased high-frequency carrier signals are applied to the fixed electrodes of the sensing capacitor and biasing signals are applied to the fixed electrodes of the actuator capacitor (52). When a force is applied to the sensor, the capacitance of the sensing capacitor changes and the carrier signal, with its amplitude and phase modulated in accordance with the magnitude and direction of the force, appears on the movable mass (10). The signal on the mass (10) is fed back to the fixed electrodes of the sensing capacitor to minimize electrostatic forces between the electrodes of the sensing capacitor. Using a separate negative feedback loop, a signal is fed back to the mass to generate electrostatic forces between the mass and the fixed electrodes of the actuator capacitor to restore the mass (10) to its original position.

Abstract translation: 用于最小化基于电容的传感器电路中的静电力的电路。 传感器包括形成两个差分电容器的中心电极的可移动质量块（10），感测差分电容器（24）和致动器差分电容器（52）。 每个差分电容器的另外两个电极（18,20,46,48）是固定的。 相反的相位高频载波信号被施加到感测电容器的固定电极，并且偏置信号被施加到致动器电容器（52）的固定电极。 当对传感器施加力时，感测电容器的电容变化，并且其载波信号（其幅度和相位根据力的大小和方向调制）出现在可移动质量块（10）上。 质量（10）上的信号被反馈到感测电容器的固定电极，以最小化感测电容器的电极之间的静电力。 使用单独的负反馈回路，将信号反馈到质量块，以在致动器电容器的质量块和固定电极之间产生静电力，以将质量（10）恢复到其初始位置。

公开(公告)号：WO1995031038A1

公开(公告)日：1995-11-16

申请号：PCT/US1995005874

申请日：1995-05-09

Applicant: ANALOG DEVICES, INC. ,  GILBERT, Barrie ,  SHU, Shao-Feng

Inventor： ANALOG DEVICES, INC.

IPC: H03H11/26

CPC classification number: H03H11/26 ,  H03K5/133

Abstract: A quasi-passive switched capacitor delay line includes a predetermined number of passive switched capacitor delay stages (Q1/Q2/C1, Q3/Q4/C2, Q5/Q6/C3, Q7/Q8/C4) and an amplifier (A1). The control terminal of each first transistor (Q1, Q3, Q5, Q7) in each delay stage receives a unique clock phase and the control terminal of each second transistor (Q2, Q4, Q6, Q8) of the same stage receives a different clock phase wherein the clock phase received by each second transistor is delayed by two clock cycles from the clock phase received by each respective first transistor.

Abstract translation: 准无源开关电容器延迟线包括预定数量的无源开关电容器延迟级（Q1 / Q2 / C1，Q3 / Q4 / C2，Q5 / Q6 / C3，Q7 / Q8 / C4）和放大器（A1）。 每个延迟级中每个第一晶体管（Q1，Q3，Q5，Q7）的控制端接收唯一的时钟相位，同一级的每个第二晶体管（Q2，Q4，Q6，Q8）的控制端接收不同的时钟 其中由每个第二晶体管接收的时钟相位从由每个相应的第一晶体管接收的时钟相位延迟两个时钟周期。

公开(公告)号：WO1995012115A1

公开(公告)日：1995-05-04

申请号：PCT/US1994012142

申请日：1994-10-25

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, A., Paul

IPC: G01K07/01

CPC classification number: G05F3/30 ,  G01K7/01 ,  Y10S323/907

Abstract: A two terminal temperature transducer which controls its operating current to indicate the temperature, by producing a linear response to temperature which can be set to extrapolate to a desired temperature. The transducer including circuitry which controls its operating current to be linearly proportional with temperature. The circuitry operates to produce a first reference voltage which is proportional to absolute temperature, produce a second reference voltage which is complementary to absolute temperature, generate a voltage drop corresponding to the operating current, compare the voltage drop to a temperature sensitive voltage corresponding to the difference between the first reference voltage and the second reference voltage, and adjust the operating current so as to equilibrate the voltage drop and the temperature sensitive voltage. According to one embodiment, the transducer includes an amplifier with a PTAT input offset voltage to drive a temperature proportional current through a series resistor, and includes circuitry to offset one input of the amplifier so as to cause the extrapolated slope of the temperature proportional current to pass through zero at a selected temperature.

Abstract translation: 通过产生对温度的线性响应来控制其工作电流以指示温度的两端温度传感器，其可以被设置为推断到期望的温度。 换能器包括控制其工作电流与温度成线性比例的电路。 该电路用于产生与绝对温度成比例的第一参考电压，产生与绝对温度互补的第二参考电压，产生对应于工作电流的电压降，将电压降与对应于 第一参考电压和第二参考电压之间的差异，并且调节工作电流以平衡电压降和温度敏感电压。 根据一个实施例，换能器包括具有PTAT输入偏移电压的放大器，以驱动通过串联电阻器的温度成比例电流，并且包括用于偏移放大器的一个输入的电路，以便使温度成比例的电流的外推斜率 在选定的温度下通过零点。

公开(公告)号：WO1995008221A1

公开(公告)日：1995-03-23

申请号：PCT/US1994010269

申请日：1994-09-13

Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A. ,  SOBOL, James, M.

Inventor： ANALOG DEVICES, INC.

IPC: H03M01/66

CPC classification number: H03H17/06 ,  H03H17/0614 ,  H03H17/0628 ,  H03L7/08 ,  H03L7/093 ,  H03L7/0992 ,  H03L2207/50 ,  H03M3/372 ,  H03M3/50

Abstract: A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator.

Abstract translation: 一种使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。 本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。 在一个实施例中，数字数据被内插固定比率，然后在Σ-Δ调制频率选择信号的控制下抽取，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率。 在另一个实施例中，数字数据在Σ-Δ调制频率选择信号的控制下进行内插，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率，然后以固定比率抽取。 使用第n级m位Σ-Δ调制器来调制频率信号选择数。 因此，数据因此在第n级m位Σ-Δ调制器的时钟速率下从内插/抽取处理中出现。 该方法和装置将输入的数字数据流的数据速率转换为第n阶m位Σ-Δ调制器的数据速率。

公开(公告)号：WO1994023502A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003780

申请日：1994-04-06

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  FERGUSON, Paul, F. Jr.

IPC: H03M01/66

CPC classification number: H03M3/34 ,  H03M3/342 ,  H03M3/464

Abstract: A switched capacitor one-bit digital-to-analog converter (10) is preferably utilized in the feedback path of a sigma delta modulator. The one-bit digital-to-analog converter (10) includes first and second capacitors (70, 72), a first switching circuit (74) for coupling charge from a reference source to the capacitors, and a second switching circuit (80) for coupling charge from the capacitors to positive and negative outputs, such as the summing junction of an operational amplifier. The switches in the second switching circuit (80) have a cross-coupled configuration and are controlled by data dependent control signals. The data dependent control signals are structured such that charge is coupled from the capacitors to the summing junction on both clock phases, regardless of the state of the data. As a result, the sizes of the capacitors can be reduced by a factor of two for the same charge transfer.

Abstract translation: 开关电容器1位数模转换器（10）优选地用于Σ-Δ调制器的反馈路径。 一位数模转换器（10）包括第一和第二电容器（70,72），用于将电荷从参考源耦合到电容器的第一开关电路（74）和第二开关电路（80） 用于将来自电容器的电荷耦合到正输出和负输出，例如运算放大器的求和结。 第二开关电路（80）中的开关具有交叉耦合配置，并且由数据相关的控制信号控制。 数据相关的控制信号被构造成使得电荷在两个时钟相位上从电容器耦合到求和结点，而与数据的状态无关。 结果，对于相同的电荷转移，电容器的尺寸可以减少2倍。

公开(公告)号：WO1993025002A1

公开(公告)日：1993-12-09

申请号：PCT/US1993004869

申请日：1993-05-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K07/08

CPC classification number: H04J3/1676 ,  H03K7/08 ,  H04L25/4902

Abstract: A dynamically selectable multimode pulse width modulation system (100) includes ramp generator means (108) for generating a ramp; pulse edge modulation means (106) responsive to the ramp generator means (108) for defining a leading edge modulated pulse, a trailing edge modulated pulse and a dual edge modulated pulse; and mode selection means (122) responsive to the pulse edge modulation means (106) for selecting one of the leading edge modulation, trailing edge modulation, and dual edge modulation modes of pulse width modulation.

公开(公告)号：WO1993025000A1

公开(公告)日：1993-12-09

申请号：PCT/US1993004867

申请日：1993-05-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K07/08

CPC classification number: H03K7/08 ,  H03K5/01

Abstract: A ramp generator (108) generates a ramp signal having a ramp portion; a latch signal generator (110) provides a latch signal coincident with the ramp portion; an indicator circuit (116, 134) indicates the desired width of a pulse to be generated; a pulse edge modulator (106) responsive to the ramp portion and to the indicator circuit provides a pulse width modulated pulse and includes one or both of a fill circuit (260) and a blanking circuit (262). The fill circuit (260) gates the latch signal when a maximum width pulse has been indicated and combines the latch signal and the pulse width modulated pulse to produce a maximum width pulse. The blanking circuit (262) gates the latch signal when a zero width pulse is indicated and inhibits the pulse width modulated pulse to produce a zero width pulse.

公开(公告)号：WO1993024996A1

公开(公告)日：1993-12-09

申请号：PCT/US1993004954

申请日：1993-05-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K03/02

CPC classification number: H03K3/0231 ,  H03K4/502

Abstract: An automatic calibration (10) for a ramp voltage generator includes a ramp voltage generator circuit (12) responsive to a clock signal (18) for providing a ramp voltage (108) during a ramp voltage period; comparator means (110) responsive to the ramp voltage for indicating whether the ramp voltage has reached a predetermined reference voltage level (112) in the ramp voltage period; and a ramp rate control circuit (26) responsive to the comparator means (110) for adjusting the ramp voltage generator circuit (12) to drive the ramp voltage (108) to obtain the predetermined reference voltage level (112) in the ramp voltage period.

公开(公告)号：WO1993022833A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004033

申请日：1993-04-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K04/08

CPC classification number: H03K4/50

Abstract: An improved ramp generator system includes a plurality of ramp generator circuits; a ramp rate signal source (44) for controlling the ramp slope; a ramp voltage signal source (46) for establishing the starting voltage of the ramp; a ramp starting signal source (42) for starting the ramp; a device for defining a plurality of ramp periods; and a switching device, responsive to the device for defining the ramp periods, alternately, sequentially connecting the ramp rate signal source, ramp voltage signal source, and ramp starting signal source, to each of the ramp generator circuits for producing a series of identical ramps.

Abstract translation: 改进的斜坡发生器系统包括多个斜坡发生器电路; 用于控制斜坡斜坡的斜坡率信号源（44）; 斜坡电压信号源（46），用于建立斜坡的起始电压; 斜坡启动信号源（42），用于启动斜坡; 用于定义多个斜坡周期的装置; 以及开关装置，响应于用于定义斜坡周期的装置，交替地将斜坡率信号源，斜坡电压信号源和斜坡起始信号源顺序地连接到每个斜坡发生器电路，以产生一系列相同的斜坡 。

公开(公告)号：WO1993022622A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004212

申请日：1993-05-05

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  DeVITO, Lawrence, M. ,  BROKAW, A., Paul

IPC: G01D05/22

CPC classification number: G01D5/2291 ,  G01D5/2216 ,  G06G7/161

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p = K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude. In another embodiment, the decoder calculates the function K A/B using similar circuitry.

Abstract translation: 用于线性可变差动变压器（LVDT）位置传感器的单片接口电路。 接口电路包括用于向LVDT初级绕组提供可选频率和幅度的激励信号的驱动电路。 接口电路还包括响应于在LVDT次级绕组中感应的信号的解码器，用于计算LVDT磁芯的位置p作为等式p = K（AB）/（A + B）的解，其中A和B表示 在初级绕组中感应的信号和K是恒定比例因子。 解码器包括用于对二次信号进行整流和滤波的电路，响应于检测信号的电荷平衡环路，用于提供具有表示B /（A + B）的占空比的二进制信号，以及响应二进制信号的输出电路， 提供位置输出。 解码器提供优异的比例因子稳定性和线性度，并且对初级驱动幅度的变化相对不敏感。 在另一个实施例中，解码器使用类似的电路来计算功能K A / B。