公开(公告)号：US11858265B2

公开(公告)日：2024-01-02

申请号：US17985590

申请日：2022-11-11

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Erik D. Ness

IPC: B41J29/393 ,  B41J2/045

CPC classification number: B41J2/04541 ,  B41J2/04543 ,  B41J2/04586

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.

公开(公告)号：US20230356524A1

公开(公告)日：2023-11-09

申请号：US18222354

申请日：2023-07-14

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: B41J2/045

CPC classification number: B41J2/04536 ,  B41J2/04586 ,  B41J2/04541

Abstract: A fluid ejection device includes a plurality of fluid actuation devices, a plurality of memory cells, and a configuration register. Each memory cell of the plurality of memory cells corresponds to a fluid actuation device of the plurality of fluid actuation devices. The configuration register stores data to enable or disable access to the plurality of memory cells.

公开(公告)号：US11787172B2

公开(公告)日：2023-10-17

申请号：US16956701

申请日：2019-02-06

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael Gardner ,  Scott A. Linn ,  John Rossi ,  Erik D. Ness

IPC: B41J29/38 ,  B41J2/045 ,  B41J2/14 ,  G11C13/00

CPC classification number: B41J2/04541 ,  B41J2/0458 ,  B41J2/04521 ,  B41J2/04581 ,  B41J2/14072 ,  B41J2/14201 ,  B41J2002/14491 ,  G11C13/0069

Abstract: A communicating print component a print head comprising a number of memory bits and a single lane analog bus conductively coupling the number of memory bits to a pad located on the exterior of the print head. The pad is to transmit an electrical signal from the number of memory bits, wherein the electrical signal indicates a combination of all selected bits of the number of memory bits.

公开(公告)号：US11760085B2

公开(公告)日：2023-09-19

申请号：US16768046

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: B41J29/38 ,  B41J2/045

CPC classification number: B41J2/04541 ,  B41J2/04586

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a configuration register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface and a data interface. The control logic enables writing to the configuration register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface.

公开(公告)号：US11731419B2

公开(公告)日：2023-08-22

申请号：US17748913

申请日：2022-05-19

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. Linn ,  James Michael Gardner ,  Michael W. Cumbie

IPC: B41J29/38 ,  B41J2/045

CPC classification number: B41J2/04541 ,  B41J2/04586

Abstract: A fluid ejection die includes a plurality of first memory cells, a plurality of first storage elements, and control logic. Each first memory cell stores a customization bit. Each first storage element is coupled to a corresponding first memory cell. The control logic, in response to a reset signal, reads the customization bit stored in each first memory cell and latches each customization bit in a corresponding first storage element.

公开(公告)号：US11613118B2

公开(公告)日：2023-03-28

申请号：US17739866

申请日：2022-05-09

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Eric Martin ,  Scott A. Linn ,  James Michael Gardner

IPC: B41J2/045 ,  B41J2/16

Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays, proximate to a number of fluid feed holes. A number of address lines are disposed proximate to a number of logic circuits on a low-voltage side of the fluid feed holes. An address decoder circuit is coupled to at least a portion of the address lines to select a fluidic actuator in a fluidic actuator array for firing. The address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array. A logic circuit triggers a driver circuit located in a high-voltage side of the plurality of fluid feed holes opposite the low-voltage side, based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.

公开(公告)号：US20230057710A1

公开(公告)日：2023-02-23

申请号：US18045258

申请日：2022-10-10

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Erik D. Ness ,  James Michael Gardner

IPC: B41J2/045

Abstract: In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.

公开(公告)号：US20230034348A1

公开(公告)日：2023-02-02

申请号：US17961476

申请日：2022-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US11364724B2

公开(公告)日：2022-06-21

申请号：US16768628

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael Gardner ,  David B. Novak

IPC: B41J2/175 ,  B41J2/045 ,  G06F13/42 ,  G06F21/44 ,  G06F1/12 ,  G06F1/08 ,  H03K19/0175 ,  B33Y30/00 ,  B29C64/259 ,  G06F3/12 ,  G01F23/24 ,  G01F23/80

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit including a memory storing a reference parameter. The at least one logic circuit is configured to receive, via the interface, a first request sent to a first address to read the reference parameter; and transmit, via the interface, the reference parameter in response to the first request. The at least one logic circuit is configured to receive, via the interface, a second request sent to a second address to implement a task; and implement the task to output a digital value via the interface in response to the second request. The reference parameter corresponds to the digital value.

公开(公告)号：US11345145B2

公开(公告)日：2022-05-31

申请号：US16766521

申请日：2019-02-06

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Eric Martin ,  Scott A. Linn ,  James Michael Gardner

IPC: B41J2/045 ,  B41J2/16

Abstract: A die for a printhead is provided in examples. The die includes a number of fluidic actuator arrays, proximate to a number of fluid feed holes. A number of address lines are disposed proximate to a number of logic circuits on a low-voltage side of the fluid feed holes. An address decoder circuit is coupled to at least a portion of the address lines to select a fluidic actuator in a fluidic actuator array for firing. The address decoder circuit is customized to select a different address for each fluidic actuator in the fluidic actuator array. A logic circuit triggers a driver circuit located in a high-voltage side of the plurality of fluid feed holes opposite the low-voltage side, based, at least in part, on a bit value for the fluidic actuator array, the fluidic actuator selected by the address decoder circuit, and a firing signal.