公开(公告)号：JP2010267964A

公开(公告)日：2010-11-25

申请号：JP2010109553

申请日：2010-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YUAN JUN ,  YIN HAIZHOU ,  LIANG YUE ,  YU XIAOJUN ,  FANG SUNFEI ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7835 ,  Y10S257/90

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric semiconductor device, and to provide a method using a spacer scheme in manufacturing the same. SOLUTION: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high-k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high-k gate dielectric, while, in other embodiments, the first and second conductive spacers are in direct contact with the threshold voltage adjusting material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非对称半导体器件，并提供一种使用间隔方案制造该方法的方法。 解决方案：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的不对称栅极堆叠。 非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。 不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而非对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。 在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物与阈值电压调节材料直接接触。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010245522A

公开(公告)日：2010-10-28

申请号：JP2010070091

申请日：2010-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  LIDIJA SEKARIC ,  TYMON BARWICZ

IPC: H01L29/786 ,  B82B1/00 ,  B82B3/00 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a p-type semiconductor nanowire device and an n-type semiconductor nanowire device for achieving a high on current and a low off current. SOLUTION: In semiconductor structures each including semiconductor link sections 30C, 50C and two adjacent pad sections 30A, 30B, 50A, 50B, the sidewalls of the semiconductor link sections are oriented to maximize hole mobility for a first semiconductor structure, and to maximize electron mobility for a second semiconductor structure. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link sections at different rates for each different crystal orientation. The widths of the semiconductor link sections are predetermined such that the different amount of thinning results in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed without excessive thinning or insufficient thinning. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于实现高导通电流和低截止电流的p型半导体纳米线器件和n型半导体纳米线器件。 解决方案：在包括半导体连接部分30C，50C和两个相邻焊盘部分30A，30B，50A，50B的半导体结构中，半导体连接部分的侧壁被取向为使第一半导体结构的空穴迁移率最大化，并且 使第二半导体结构的电子迁移率最大化。 通过半导体结构的氧化来减薄，对于每个不同的晶体取向，半导体连接部分的宽度以不同的速率减小。 半导体连接部分的宽度是预定的，使得不同的稀化量导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。 通过补偿不同晶面的不同稀化速率，可以形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不足够的稀化。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007142429A

公开(公告)日：2007-06-07

申请号：JP2006310926

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  KERN LIM ,  GREENE BRIAN J

IPC: H01L29/78 ,  H01L21/316 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having dielectric stressor elements and a method for manufacturing the same.
SOLUTION: There is provided a chip including an active semiconductor region and a field effect transistor (FET) having a channel region, a source region, and a drain region, all of which are arranged in the active semiconductor region. The FET has a lengthwise direction in the direction of the length of the channel region and a transverse direction in the direction of the width of the channel region. An embedded dielectric stressor element has an upper surface extending horizontally at a first depth below the main surface of a part of the active semiconductor region, such as an east edge portion of the active semiconductor region. Surface dielectric stressor elements are arranged adjacent to each other in the transverse direction in the active semiconductor region on the main surface of the active semiconductor region. The surface dielectric stressor element extends from the main surface to a second depth substantially not deeper than the first depth. The stresses applied by the embedded dielectric stressor element and the surface dielectric stressor element collaborate in applying shearing stress to the channel region of the FET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有介电应力元件的半导体器件及其制造方法。 解决方案：提供了包括有源半导体区域的芯片和具有沟道区域，源极区域和漏极区域的场效应晶体管（FET），它们都被布置在有源半导体区域中。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 嵌入式介电应力元件具有在有源半导体区域的一部分（例如有源半导体区域的东缘部分）的主表面下方的第一深度处水平延伸的上表面。 表面介质应力元件在有源半导体区域的主表面上的有源半导体区域中沿横向彼此相邻布置。 表面介电应力元件从主表面延伸到基本不深于第一深度的第二深度。 嵌入的介电应力元件和表面介电应力元件施加的应力协同作用，对FET的沟道区域施加剪切应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006074040A

公开(公告)日：2006-03-16

申请号：JP2005247839

申请日：2005-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  GREGORY G FREEMAN ,  KHATER MARWAN H

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance bipolar device and its manufacturing method.
SOLUTION: The method to increase electronic charge carrier mobility in a bipolar device includes the steps of generating compression strain in the device to increase hole mobility on the device's internal base, and causing tensile strain in the device to increase electron mobility on the internal base of the device. The compression strain and tensile strain are generated by forming a stress layer in the neighborhood of the internal base of the device. As for the stress layer, at least part of it is adjacent to an emitter structure of the device, and is imbedded in the device's base layer. The stress layer has a grating constant different from the internal base.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高性能双极器件及其制造方法。 解决方案：在双极器件中增加电子载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件内部基极上的空穴迁移率，并引起器件中的拉伸应变以增加电子迁移率 设备的内部基座。 压缩应变和拉伸应变通过在器件的内部基部附近形成应力层来产生。 至于应力层，其至少一部分与器件的发射极结构相邻，并嵌入器件的基极层。 应力层具有不同于内部基底的光栅常数。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005175495A

公开(公告)日：2005-06-30

申请号：JP2004357623

申请日：2004-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method of manufacturing using tensile stress and compressive stress.
SOLUTION: The method of manufacturing includes a step of forming shallow trench isolation (STI) in a substrate, and a step of providing a first material and a second material on the substrate. The first material and the second material form a first island and a second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layers prior to forming finFETs. A Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask. The hard mask becomes a capping layer, which is under tension, preventing lateral buckling of the nFETfin.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供使用拉伸应力和压缩应力的半导体结构和制造方法。 解决方案：制造方法包括在衬底中形成浅沟槽隔离（STI）的步骤，以及在衬底上提供第一材料和第二材料的步骤。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层。 硬掩模成为一个处于张力下的覆盖层，可防止nFETfin的横向屈曲。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005109474A

公开(公告)日：2005-04-21

申请号：JP2004275965

申请日：2004-09-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H

IPC: H01L21/205 ,  C30B1/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/322 ,  H01L21/324 ,  H01L21/36 ,  H01L29/10

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/1054

Abstract: PROBLEM TO BE SOLVED: To provide an effective manufacturing method of a loosened SiGe layer. SOLUTION: A compressed distortional SiGe layer is formed on a silicon substrate. An EOR damage is given by performing an ionic injection of atoms onto the SiGe layer. Annealing is performed to loosen the distorted SiGe layer. An interstitial dislocation loop is formed as uniformly distributed in the SiGe layer during the annealing. The interstitial dislocation loop is a base for the nucleation of the misfit dislocation between the SiGe layer and the silicon substrate. Since the interstitial dislocation loop is uniformly distributed, the misfit dislocation is uniformly distributed as well, thereby the SiGe layer is loosened. The tensile distortional silicon layer is formed on the loosened SiGe layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供松散的SiGe层的有效的制造方法。 解决方案：在硅衬底上形成压缩失真的SiGe层。 通过对SiGe层进行离子注入原子来给出EOR损伤。 进行退火以松动失真的SiGe层。 在退火期间，间隙位错环形成均匀分布在SiGe层中。 间隙位错环是SiGe层和硅衬底之间失配位错成核的基础。 由于间隙位错环均匀分布，因此失配位错也均匀分布，SiGe层松动。 拉伸失真硅层形成在松散的SiGe层上。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005094005A

公开(公告)日：2005-04-07

申请号：JP2004266297

申请日：2004-09-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMA ,  GLUSCHENKOV OLEG G

IPC: H01L21/8242 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure of a vertical strained silicon device.
SOLUTION: A trench capacitor vertical-transistor DRAM cell in an SiGe wafer compensates for overhang of a pad nitride, by forming an epitaxial strained silicon layer on trench walls that improves transistor mobility, removes voids from the polysilicon filling, and reduces resistance on the bit line contact. Another feature is that by forming a vertical strained silicon channel, the performance of the vertical device is improved.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供垂直应变硅器件的方法和结构。 解决方案：SiGe晶片中的沟槽电容器垂直晶体管DRAM单元通过在沟槽壁上形成外延应变硅层来补偿衬垫氮化物的突出，从而提高晶体管的迁移率，去除多晶硅填充物的空隙，并降低电阻 在位线上联系。 另一个特征是通过形成垂直应变硅通道，提高了垂直装置的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：WO2007140288A3

公开(公告)日：2008-04-24

申请号：PCT/US2007069720

申请日：2007-05-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76283

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Abstract translation: 本发明涉及具有器件区域（2,4,6）的绝缘体上绝缘体（SOI）衬底，每个衬底半导体衬底层（12）和半导体器件层（16）和掩埋绝缘体层（14） ）之间。 由垂直绝缘柱（22）支撑的半导体器件层（16）各自具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由垂直绝缘柱（ 22）。 气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

公开(公告)号：WO2005043591A3

公开(公告)日：2007-06-21

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。