公开(公告)号：JP2005175480A

公开(公告)日：2005-06-30

申请号：JP2004353535

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN C ,  CHIDAMBARRAO DURESETI ,  LI YUJUN ,  SETTLEMYER KENNETH T JR

IPC: H01L21/308 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a FinFET which allows an integrated circuit or an electronic device that includes smaller, more densely disposed active regions or active lines.
SOLUTION: A method of forming an integrated circuit having a FinFET comprises a method of forming sub-lithographic fins. A silicon block is defined by a mask, and a pair of fins which is reduced in width or pulled back by the thickness of one fin on each side is included. After that, a second mask is formed around the first mask so that an aperture having the width of the separation distance between the pair of fins remains in the second mask after the first mask is removed. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining the fin thickness by the pullback step.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种FinFET，其允许集成电路或包括更小，更密集布置的有源区或有源线的电子器件。 解决方案：一种形成具有FinFET的集成电路的方法包括形成亚光刻鳍片的方法。 硅块由掩模限定，并且包括在每侧具有一个翅片的宽度减小或拉回的一对翅片。 之后，在第一掩模周围形成第二掩模，使得在去除第一掩模之后，具有一对散热片之间的间隔距离的宽度的孔保持在第二掩模中。 当通过孔蚀刻硅时，翅片被第二掩模保护，从而通过回拉步骤限定翅片厚度。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004111957A

公开(公告)日：2004-04-08

申请号：JP2003310635

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEGDE SURYANARAYAN G ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide the structure and the method of forming an integrated circuit including a low programming voltage anti-fuse on a semiconductor substrate. SOLUTION: This integrated circuit is formed by doping a part of a semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric that is destroyed by the application of breakdown voltage on the doped portion of the semiconductor substrate, forming a first conductor that is separated from the semiconductor substrate by the thin dielectric, and forming a second conductor that is conductively connected with the doped portion of the semiconductor substrate. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：WO2007025259A2

公开(公告)日：2007-03-01

申请号：PCT/US2006033582

申请日：2006-08-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

Inventor： CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

IPC: H01L29/00

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/165

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having abase region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 ran thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract translation: 本发明涉及一种具有其中含SiGe的层的碱性区的高性能异质结双极晶体管（HBT）。 含SiGe的层的厚度不超过约100埃，具有预定的临界锗含量。 含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量本发明还涉及通过均匀增加的具有含SiGe的基底层来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法 基底层中的锗含量，使得其中的平均锗含量不小于基于基底层的厚度计算的临界锗含量的80％，条件是基底层不大于100nm厚。

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：JP2010267964A

公开(公告)日：2010-11-25

申请号：JP2010109553

申请日：2010-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YUAN JUN ,  YIN HAIZHOU ,  LIANG YUE ,  YU XIAOJUN ,  FANG SUNFEI ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7835 ,  Y10S257/90

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric semiconductor device, and to provide a method using a spacer scheme in manufacturing the same. SOLUTION: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high-k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high-k gate dielectric, while, in other embodiments, the first and second conductive spacers are in direct contact with the threshold voltage adjusting material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非对称半导体器件，并提供一种使用间隔方案制造该方法的方法。 解决方案：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的不对称栅极堆叠。 非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。 不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而非对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。 在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物与阈值电压调节材料直接接触。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010245522A

公开(公告)日：2010-10-28

申请号：JP2010070091

申请日：2010-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  LIDIJA SEKARIC ,  TYMON BARWICZ

IPC: H01L29/786 ,  B82B1/00 ,  B82B3/00 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0673 ,  H01L29/125 ,  H01L29/42392 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a p-type semiconductor nanowire device and an n-type semiconductor nanowire device for achieving a high on current and a low off current. SOLUTION: In semiconductor structures each including semiconductor link sections 30C, 50C and two adjacent pad sections 30A, 30B, 50A, 50B, the sidewalls of the semiconductor link sections are oriented to maximize hole mobility for a first semiconductor structure, and to maximize electron mobility for a second semiconductor structure. Thinning by oxidation of the semiconductor structures reduces the width of the semiconductor link sections at different rates for each different crystal orientation. The widths of the semiconductor link sections are predetermined such that the different amount of thinning results in target sublithographic dimensions for the resulting semiconductor nanowires after thinning. By compensating for different thinning rates for different crystallographic surfaces, semiconductor nanowires having optimal sublithographic widths may be formed without excessive thinning or insufficient thinning. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于实现高导通电流和低截止电流的p型半导体纳米线器件和n型半导体纳米线器件。 解决方案：在包括半导体连接部分30C，50C和两个相邻焊盘部分30A，30B，50A，50B的半导体结构中，半导体连接部分的侧壁被取向为使第一半导体结构的空穴迁移率最大化，并且 使第二半导体结构的电子迁移率最大化。 通过半导体结构的氧化来减薄，对于每个不同的晶体取向，半导体连接部分的宽度以不同的速率减小。 半导体连接部分的宽度是预定的，使得不同的稀化量导致在变薄后得到的半导体纳米线的目标亚光刻尺寸。 通过补偿不同晶面的不同稀化速率，可以形成具有最佳亚光刻宽度的半导体纳米线，而不会过度稀化或不足够的稀化。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007142429A

公开(公告)日：2007-06-07

申请号：JP2006310926

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  KERN LIM ,  GREENE BRIAN J

IPC: H01L29/78 ,  H01L21/316 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having dielectric stressor elements and a method for manufacturing the same.
SOLUTION: There is provided a chip including an active semiconductor region and a field effect transistor (FET) having a channel region, a source region, and a drain region, all of which are arranged in the active semiconductor region. The FET has a lengthwise direction in the direction of the length of the channel region and a transverse direction in the direction of the width of the channel region. An embedded dielectric stressor element has an upper surface extending horizontally at a first depth below the main surface of a part of the active semiconductor region, such as an east edge portion of the active semiconductor region. Surface dielectric stressor elements are arranged adjacent to each other in the transverse direction in the active semiconductor region on the main surface of the active semiconductor region. The surface dielectric stressor element extends from the main surface to a second depth substantially not deeper than the first depth. The stresses applied by the embedded dielectric stressor element and the surface dielectric stressor element collaborate in applying shearing stress to the channel region of the FET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有介电应力元件的半导体器件及其制造方法。 解决方案：提供了包括有源半导体区域的芯片和具有沟道区域，源极区域和漏极区域的场效应晶体管（FET），它们都被布置在有源半导体区域中。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 嵌入式介电应力元件具有在有源半导体区域的一部分（例如有源半导体区域的东缘部分）的主表面下方的第一深度处水平延伸的上表面。 表面介质应力元件在有源半导体区域的主表面上的有源半导体区域中沿横向彼此相邻布置。 表面介电应力元件从主表面延伸到基本不深于第一深度的第二深度。 嵌入的介电应力元件和表面介电应力元件施加的应力协同作用，对FET的沟道区域施加剪切应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006074040A

公开(公告)日：2006-03-16

申请号：JP2005247839

申请日：2005-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  GREGORY G FREEMAN ,  KHATER MARWAN H

IPC: H01L21/331 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a high-performance bipolar device and its manufacturing method.
SOLUTION: The method to increase electronic charge carrier mobility in a bipolar device includes the steps of generating compression strain in the device to increase hole mobility on the device's internal base, and causing tensile strain in the device to increase electron mobility on the internal base of the device. The compression strain and tensile strain are generated by forming a stress layer in the neighborhood of the internal base of the device. As for the stress layer, at least part of it is adjacent to an emitter structure of the device, and is imbedded in the device's base layer. The stress layer has a grating constant different from the internal base.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种高性能双极器件及其制造方法。 解决方案：在双极器件中增加电子载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件内部基极上的空穴迁移率，并引起器件中的拉伸应变以增加电子迁移率 设备的内部基座。 压缩应变和拉伸应变通过在器件的内部基部附近形成应力层来产生。 至于应力层，其至少一部分与器件的发射极结构相邻，并嵌入器件的基极层。 应力层具有不同于内部基底的光栅常数。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005175495A

公开(公告)日：2005-06-30

申请号：JP2004357623

申请日：2004-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and a method of manufacturing using tensile stress and compressive stress.
SOLUTION: The method of manufacturing includes a step of forming shallow trench isolation (STI) in a substrate, and a step of providing a first material and a second material on the substrate. The first material and the second material form a first island and a second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layers prior to forming finFETs. A Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask. The hard mask becomes a capping layer, which is under tension, preventing lateral buckling of the nFETfin.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供使用拉伸应力和压缩应力的半导体结构和制造方法。 解决方案：制造方法包括在衬底中形成浅沟槽隔离（STI）的步骤，以及在衬底上提供第一材料和第二材料的步骤。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层。 硬掩模成为一个处于张力下的覆盖层，可防止nFETfin的横向屈曲。 版权所有（C）2005，JPO＆NCIPI