公开(公告)号：US09792190B2

公开(公告)日：2017-10-17

申请号：US14752585

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  George Vergis

IPC: G06F11/20 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F11/2069 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/00 ,  G06F11/3034 ,  G06F11/3058 ,  G06F2201/82

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

公开(公告)号：US09645829B2

公开(公告)日：2017-05-09

申请号：US14319361

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Adam J. Brooks ,  George Vergis

IPC: G06F11/14 ,  G06F9/44 ,  G06F11/20

CPC classification number: G06F9/4401 ,  G06F11/1441 ,  G06F11/2015

Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.

公开(公告)号：US12106818B2

公开(公告)日：2024-10-01

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. Pious ,  Raji James ,  Phani K. Alaparthi ,  George Vergis ,  Bill Nale ,  Konika Ganguly

IPC: G11C5/14 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G11C11/4074

CPC classification number: G11C5/148 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3296 ,  G11C5/141 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

公开(公告)号：US20220214981A1

公开(公告)日：2022-07-07

申请号：US17705439

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/16 ,  G06F12/06 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

公开(公告)号：US11056179B2

公开(公告)日：2021-07-06

申请号：US16737666

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Chong J. Zhao ,  James A. McCall ,  Shigeki Tomishima ,  George Vergis ,  Kuljit S. Bains

IPC: G11C29/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

公开(公告)号：US10970239B2

公开(公告)日：2021-04-06

申请号：US15970639

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Kenneth Foust ,  George Vergis

IPC: G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G06F13/42 ,  G06F1/18 ,  G11C7/22 ,  G11C5/04

Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

公开(公告)号：US10943640B2

公开(公告)日：2021-03-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

公开(公告)号：US10923859B2

公开(公告)日：2021-02-16

申请号：US16389781

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  Jun Liao ,  Xiang Li ,  George Vergis ,  Christopher E. Cox

IPC: H01R13/6471 ,  H05K5/00 ,  H05K5/02 ,  H01R12/73 ,  H05K1/18 ,  H01R12/70 ,  H01R12/72 ,  H01R13/6461 ,  H01R13/24

Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

公开(公告)号：US10783048B2

公开(公告)日：2020-09-22

申请号：US15728414

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  George Vergis

IPC: G06F11/20 ,  G06F3/06 ,  G06F11/30 ,  G06F11/14 ,  G06F11/00

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

公开(公告)号：US10727618B2

公开(公告)日：2020-07-28

申请号：US16316586

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis

IPC: H01R12/58 ,  H01R12/57 ,  H01R12/70 ,  H01R12/73 ,  H01R13/633 ,  H05K1/14

Abstract: Anchoring power pins are described herein. In one embodiment, a system includes a circuit board including a through hole, and a connector for coupling a module with the circuit board. The connector includes housing including a module-facing side to receive the module and a circuit board-facing side to couple with the circuit board. The connector includes a conductive power pin to both physically anchor the connector to the circuit board and electrically couple the module with the circuit board, the conductive power pin including a tip protruding from the circuit board-facing side of the connector to extend into a matching through hole in the circuit board.