公开(公告)号：US20220406782A1

公开(公告)日：2022-12-22

申请号：US17351301

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Albert B. Chen ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Travis W. Lajoie ,  Van H. Le ,  Alekhya Nimmagadda ,  Miriam R. Reshotko ,  Hui Jae Yoo

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

Abstract: An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

公开(公告)号：US11424160B2

公开(公告)日：2022-08-23

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/02

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US11380684B2

公开(公告)日：2022-07-05

申请号：US16145817

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Abhishek Sharma ,  Patrick Morrow ,  Hui Jae Yoo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.

公开(公告)号：US20220189913A1

公开(公告)日：2022-06-16

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H01L27/108

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US10832951B2

公开(公告)日：2020-11-10

申请号：US15631701

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20200258778A1

公开(公告)日：2020-08-13

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/02 ,  H01L21/8238

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US10256141B2

公开(公告)日：2019-04-09

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Eungnak Han ,  Jasmeet S. Chawla ,  Marie Krysak ,  Hui Jae Yoo ,  Tristan A. Tronic

IPC: H01L21/331 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US09691657B2

公开(公告)日：2017-06-27

申请号：US15096609

申请日：2016-04-12

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20160307796A1

公开(公告)日：2016-10-20

申请号：US15192643

申请日：2016-06-24

Applicant: INTEL CORPORATION

Inventor： Hui Jae Yoo ,  Jeffery D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L21/3205

CPC classification number: H01L21/76834 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

公开(公告)号：US12266568B2

公开(公告)日：2025-04-01

申请号：US18535623

申请日：2023-12-11

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC: H01L21/768 ,  H01L23/532

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.