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    Cross-point magnetic random access memory with piezoelectric selector
    41.
    发明授权
    Cross-point magnetic random access memory with piezoelectric selector 有权

    公开(公告)号：US11600659B2

    公开(公告)日：2023-03-07

    申请号：US17399530

    申请日：2021-08-11

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

    One transistor and one ferroelectric capacitor memory cells in diagonal arrangements
    43.
    发明授权
    One transistor and one ferroelectric capacitor memory cells in diagonal arrangements 有权

    公开(公告)号：US11450675B2

    公开(公告)日：2022-09-20

    申请号：US16132281

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532

    Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

    BINARY-WEIGHTED CAPACITOR CHARGE-SHARING FOR MULTIPLICATION
    44.
    发明申请
    BINARY-WEIGHTED CAPACITOR CHARGE-SHARING FOR MULTIPLICATION 有权

    公开(公告)号：US20220253285A1

    公开(公告)日：2022-08-11

    申请号：US17730011

    申请日：2022-04-26

    Applicant: Intel Corporation

    Inventor： Yu-Lin Chao ,  Clifford Lu Ong ,  Dmitri E. Nikonov ,  Ian A. Young ,  Eric A. Karl

    IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/22 ,  G06N3/04

    Abstract: An analog multiplication circuit includes switched capacitors to multiply digital operands in an analog representation and output a digital result with an analog-to-digital convertor. The capacitors are arranged with a capacitance according to the respective value of the digital bit inputs. To perform the multiplication, the capacitors are selectively charged according to the first operand of the multiplication. The capacitors are then connected to a common interconnect for charge sharing across the capacitors, averaging the charge according to the charge determined by the first operand. The capacitor are then maintained or discharged according to a second operand, such that the remaining charge represents a number of “copies” of the averaged charge. The capacitors are then averaged and output for conversion by an analog-to-digital convertor. This circuit may be repeated to construct a multiply-and-accumulate circuit by combining charges from several such multiplication circuits.

    ANTI-FERROELECTRIC CAPACITOR MEMORY CELL
    45.
    发明申请
    ANTI-FERROELECTRIC CAPACITOR MEMORY CELL 有权

    公开(公告)号：US20220231035A1

    公开(公告)日：2022-07-21

    申请号：US17713790

    申请日：2022-04-05

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/11507 ,  G11C11/22 ,  H01L49/02

    Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.

    Three-dimensional oscillator structure
    47.
    发明授权
    Three-dimensional oscillator structure 有权

    公开(公告)号：US11250317B2

    公开(公告)日：2022-02-15

    申请号：US16144952

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Dmitri E. Nikonov ,  Elijah V. Karpov ,  Ian A. Young

    IPC: G06N3/063 ,  H03B5/20 ,  H01L45/00 ,  H03K4/787 ,  H03B1/02 ,  H03B7/00 ,  G06N3/04

    Abstract: Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.

    Polarization gate stack SRAM
    48.
    发明授权
    Polarization gate stack SRAM 有权

    公开(公告)号：US11232832B2

    公开(公告)日：2022-01-25

    申请号：US17061272

    申请日：2020-10-01

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

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