公开(公告)号：US10474596B2

公开(公告)日：2019-11-12

申请号：US14749893

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  John G. Holm ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: G06F13/24 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228

Abstract: In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.

公开(公告)号：US20190324811A1

公开(公告)日：2019-10-24

申请号：US16460371

申请日：2019-07-02

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Murugasamy K. Nachimuthu ,  Muralidharan Sundararajan ,  Susanne M. Balle ,  Mohan J. Kumar

IPC: G06F9/50 ,  H04L29/08

Abstract: Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

公开(公告)号：US10319458B2

公开(公告)日：2019-06-11

申请号：US15457326

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/52 ,  G11C29/04 ,  G11C29/44 ,  G11C13/00

Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.

公开(公告)号：US10296416B2

公开(公告)日：2019-05-21

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20190068698A1

公开(公告)日：2019-02-28

申请号：US15858542

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: H04L29/08 ,  G06F1/32 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for providing efficient pooling for a system that includes a hyper converged infrastructure. A sled of the system includes a network interface controller that includes a first bridge logic unit to communicatively couple to a network of bridge logic units. The first bridge logic unit is further to obtain, from a requestor device, a request to access a requested device, determine whether the requested device is on the present sled or on a remote sled different from the present sled, selectively power on, in response to a determination that the requested device is located on the present sled, the requested device, communicate, in response to a determination that the requested device is on the remote sled, with a second bridge logic unit of the remote sled, and provide, to the requestor device through the first bridge logic unit, access to the requested device

公开(公告)号：US20190044849A1

公开(公告)日：2019-02-07

申请号：US16045345

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Yadong Li ,  Michael Orr ,  Anjaneya Reddy Chagam Reddy ,  Mohan J. Kumar

IPC: H04L12/703 ,  H04L12/24 ,  H04L12/743 ,  H04L12/801 ,  H04L12/803 ,  H04L12/935 ,  H04L12/931

Abstract: Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.

公开(公告)号：US10116518B2

公开(公告)日：2018-10-30

申请号：US15599087

申请日：2017-05-18

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L12/855 ,  H04L29/12

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

公开(公告)号：US20180165196A1

公开(公告)日：2018-06-14

申请号：US15375675

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mohan J. Kumar ,  Thomas Willhalm ,  Robert G. Blankenship

IPC: G06F12/0808 ,  G06F13/16 ,  G06F3/06 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F12/0831 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/128 ,  G06F13/1663 ,  G06F2212/1024 ,  G06F2212/621

Abstract: Embodiments provide for a processor including a cache a caching agent and a processing node to decode an instruction including at least one operand specifying an address range within a distributed shared memory (DSM) and perform a flush to a first of a plurality of memory devices in the DSM at the specified address range.

公开(公告)号：US20180159722A1

公开(公告)日：2018-06-07

申请号：US15370563

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Deepak Soma Reddy ,  Mrittika Ganguli ,  Mohan J. Kumar

IPC: H04L12/24

CPC classification number: H04L41/0803 ,  H04L41/0893 ,  Y02D30/30

Abstract: Apparatus and method to dynamically compose network resources are disclosed herein. In some embodiments, a network management fabric controller may include a module, in response to a request for a network service, that is to identify a child pool included in a particular network service pool, from among a plurality of network service pools associated with respective network services, that is capable of providing the network service, the child pool comprising identification of one or more particular ports of a particular compute node switch within the network; and another module that is to establish a connection between a compute component and the one or more particular ports of the particular compute node switch and between the one or more particular ports of the particular compute node switch and one or more particular ports of the main network switch in accordance with the particular network service pool.

公开(公告)号：US09904586B2

公开(公告)日：2018-02-27

申请号：US14925131

申请日：2015-10-28

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Mohan J. Kumar ,  Hisham Shafi ,  Ron Gabor ,  Ashok Raj

IPC: G11C29/00 ,  G06F11/07 ,  G06F9/30 ,  G06F12/00

CPC classification number: G06F11/079 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3016 ,  G06F11/0721 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/0246

Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.