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    Buffer to reduce write amplification of misaligned write operations
    41.
    发明授权
    Buffer to reduce write amplification of misaligned write operations 有权

    公开(公告)号：US11861219B2

    公开(公告)日：2024-01-02

    申请号：US16712703

    申请日：2019-12-12

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Jawad B. Khan ,  Sanjeev N. Trika

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0614 ,  G06F3/0646 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0679

    Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

    Adaptive write acknowledgment for storage devices
    42.
    发明授权
    Adaptive write acknowledgment for storage devices 有权

    公开(公告)号：US11210130B2

    公开(公告)日：2021-12-28

    申请号：US16855139

    申请日：2020-04-22

    Applicant: Intel Corporation

    Inventor： Bishwajit Dutta ,  Sanjeev N. Trika ,  Anand S. Ramalingam ,  Pallav H. Gala

    IPC: G06F9/46 ,  G06F3/06 ,  G06F9/54 ,  G06F9/48

    Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.

    Dynamic reliability levels for storage devices
    44.
    发明授权
    Dynamic reliability levels for storage devices 有权

    公开(公告)号：US10700703B2

    公开(公告)日：2020-06-30

    申请号：US16022631

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Sanjeev N. Trika ,  Omesh Tickoo ,  Wei Wu

    IPC: H03M13/00 ,  H03M13/05 ,  G06F11/10

    Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.

    Apparatus, computer program product, system, and method for managing multiple regions of a memory device
    45.
    发明授权
    Apparatus, computer program product, system, and method for managing multiple regions of a memory device 有权

    公开(公告)号：US10592408B2

    公开(公告)日：2020-03-17

    申请号：US15703907

    申请日：2017-09-13

    Applicant: INTEL CORPORATION

    Inventor： Peng Li ,  Sanjeev N. Trika

    IPC: G06F12/02 ,  H04L29/08 ,  G11C16/34 ,  G11C13/00

    Abstract: Provided are an apparatus, computer program product, system, and method for managing multiple regions of a non-volatile memory device. A first group of logical bands is assigned to a first memory region in which metadata will be stored and a second group of logical bands is assigned to a second memory region to which host data is written, wherein the second group of logical bands is larger than the first group of logical bands. Physical bands are mapped to the first number of logical bands and the second number of logical bands. Indication is returned to the host system of the first and second groups of logical bands assigned to the first and second memory regions, respectively. The host system directs requests for metadata to logical addresses in the first group of logical bands and directs request for file data to logical addresses in the second group of logical bands.

    Technologies for combining logical-to-physical address table updates in a single write operation
    47.
    发明授权
    Technologies for combining logical-to-physical address table updates in a single write operation 有权

    公开(公告)号：US10528463B2

    公开(公告)日：2020-01-07

    申请号：US15278837

    申请日：2016-09-28

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

    IPC: G06F12/02 ,  G06F3/06 ,  G11C14/00

    Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

    Technologies for addressing data in a memory
    50.
    发明授权
    Technologies for addressing data in a memory 有权

    公开(公告)号：US10416900B2

    公开(公告)日：2019-09-17

    申请号：US15198015

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Vinodh Gopal ,  Sanjeev N. Trika

    IPC: G06F3/06

    Abstract: Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.

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