公开(公告)号：US20170278959A1

公开(公告)日：2017-09-28

申请号：US15511139

申请日：2014-10-30

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Sanaz Gardner ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/45 ,  H01L21/283 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L21/283 ,  H01L21/3085 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present description relates to a gallium nitride transistor which includes at least one source/drain structure having low contact resistance between a 2D electron gas of the gallium nitride transistor and the source/drain structure. The low contact resistance may be a result of at least a portion of the source/drain structure being a single-crystal structure abutting the 2D electron gas. In one embodiment, the single-crystal structure is grown with a portion of a charge inducing layer of the gallium nitride transistor acting as a nucleation site.

公开(公告)号：US09716149B2

公开(公告)日：2017-07-25

申请号：US15135441

申请日：2016-04-21

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L29/80 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/06 ,  H01L29/201 ,  H01L29/778 ,  H01L21/283 ,  H01L29/423

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20170207310A1

公开(公告)日：2017-07-20

申请号：US15326022

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz Gardner ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/41783 ,  H01L21/28587 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.

公开(公告)号：US20170133497A1

公开(公告)日：2017-05-11

申请号：US15410681

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/207 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

公开(公告)号：US09583396B2

公开(公告)日：2017-02-28

申请号：US14777730

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.

Abstract translation: 可以通过在形成在浅沟槽隔离（STI）区域的侧壁之间的沟槽的底部的衬底表面上外延生长第一层材料来形成电子器件鳍。 沟槽高度可以是其宽度的至少1.5倍，并且第一层可以填充小于沟槽高度。 然后可以在沟槽中的第一层和STI区域的顶表面上外延生长第二层材料。 第二层可以具有在沟槽上延伸的第二宽度和STI区域的顶表面的上部。 然后可以对第二层进行图案化和蚀刻，以在靠近沟槽的STI区域的顶表面的部分上形成一对电子器件散热片。 该过程可以避免由于层界面中的晶格失配导致的鳍片中的晶体缺陷。

公开(公告)号：US20160204036A1

公开(公告)日：2016-07-14

申请号：US14777730

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.

Abstract translation: 可以通过在形成在浅沟槽隔离（STI）区域的侧壁之间的沟槽的底部的衬底表面上外延生长第一层材料来形成电子器件鳍。 沟槽高度可以是其宽度的至少1.5倍，并且第一层可以填充小于沟槽高度。 然后可以在沟槽中的第一层和STI区域的顶表面上外延生长第二层材料。 第二层可以具有在沟槽上延伸的第二宽度和STI区域的顶表面的上部。 然后可以对第二层进行图案化和蚀刻，以在靠近沟槽的STI区域的顶表面的部分上形成一对电子器件散热片。 该过程可以避免由于层界面中的晶格失配导致的鳍片中的晶体缺陷。

公开(公告)号：US09219079B2

公开(公告)日：2015-12-22

申请号：US14581722

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/80 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/06 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Abstract translation: III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。 在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。 在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。 在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。 在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。

公开(公告)号：US20150318375A1

公开(公告)日：2015-11-05

申请号：US14752365

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz Kabehie GARDNER ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC: H01L29/66 ,  H01L29/205 ,  H01L21/223 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265 ,  H01L29/20 ,  H01L21/311

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US12125888B2

公开(公告)日：2024-10-22

申请号：US16642861

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/41725 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US12027613B2

公开(公告)日：2024-07-02

申请号：US16419179

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L29/20 ,  H01L29/51

CPC classification number: H01L29/7786 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0655 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/778 ,  H01L2224/0401 ,  H01L2924/13064

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.