公开(公告)号：US20240054595A1

公开(公告)日：2024-02-15

申请号：US17884755

申请日：2022-08-10

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Vasanth Ranganathan ,  James Valerio ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Ben J. Ashbaugh ,  Michal Mrozek ,  Murali Ramadoss ,  Hong Jiang ,  Ankur Shah

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06F9/3855

Abstract: Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.

公开(公告)号：US20230298129A1

公开(公告)日：2023-09-21

申请号：US17849165

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  David Cowperthwaite ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/1009 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1009 ,  G06T1/20 ,  G06F2212/302

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

公开(公告)号：US20230298128A1

公开(公告)日：2023-09-21

申请号：US17849106

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Aditya Navale ,  David Cowperthwaite

IPC: G06T1/60 ,  G06F12/1027 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/1027 ,  G06T1/20 ,  G06F2212/302 ,  G06F2212/683

Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.

公开(公告)号：US20220138895A1

公开(公告)日：2022-05-05

申请号：US17430041

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Vasanth Raganathan ,  Abhishek R. Appu ,  Ben Ashbaugh ,  Peter Doyle ,  Brandon Fliflet ,  Arthur Hunter ,  Brent Insko ,  Scott Janus ,  Altug Koker ,  Aditya Navale ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  James Valerio

IPC: G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments are generally directed to compute optimization in graphics processing. An embodiment of an apparatus includes one or more processors including a multi-tile graphics processing unit (GPU) to process data, the multi-tile GPU including multiple processor tiles; and a memory for storage of data for processing, wherein the apparatus is to receive compute work for processing by the GPU, partition the compute work into multiple work units, assign each of multiple work units to one of the processor tiles, and process the compute work using the processor tiles assigned to the work units.

公开(公告)号：US20220075746A1

公开(公告)日：2022-03-10

申请号：US17014023

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Ankur Shah ,  Joydeep Ray ,  Aditya Navale ,  Altug Koker ,  Murali Ramadoss ,  Niranjan L. Cooray ,  Jeffery S. Boles ,  Aravindh Anantaraman ,  David Puffer ,  James Valerio ,  Vasanth Ranganathan

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30 ,  G06F9/52 ,  G06F12/0837 ,  G06F12/0888

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

公开(公告)号：US10997086B1

公开(公告)日：2021-05-04

申请号：US16807430

申请日：2020-03-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Aditya Navale ,  Ankur Shah ,  Murali Ramadoss ,  Ben Ashbaugh ,  Ronald Silvas

IPC: G06F12/10 ,  G06F12/1072

Abstract: Systems and methods for providing shared virtual memory addressing support for a host system are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations. A memory management unit (MMU) is coupled to the processing resources. The MMU to support a first virtual address size for managing allocation of non-shared virtual memory and to support a second virtual address size for managing allocation of shared virtual memory that is shared between the graphics processor and a host.

公开(公告)号：US10915608B2

公开(公告)日：2021-02-09

申请号：US16126060

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Vidhya Krishnan ,  Sandeep Sodhi ,  Sreekanth Mavila ,  Altug Koker ,  Aditya Navale ,  Scott Janus ,  Changliang Wang

IPC: H04L9/00 ,  G06F21/12 ,  G06T15/00 ,  H04N21/254 ,  G06F9/48 ,  H04L9/08 ,  G06F21/60 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.

公开(公告)号：US10908939B2

公开(公告)日：2021-02-02

申请号：US15420376

申请日：2017-01-31

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Altug Koker ,  David Puffer ,  Murali Ramadoss ,  Bryan R. White ,  Hema C. Nalluri ,  Aditya Navale

IPC: G06F9/455 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engine to execute a work element using the data identifying a virtual machine or application associated with the work element, wherein different graphics engines are configured to simultaneously execute workloads belonging to different virtual machines or applications.

公开(公告)号：US10417730B2

公开(公告)日：2019-09-17

申请号：US15386111

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Vikranth Vemulapalli ,  Chandra S. Gurram ,  Aditya Navale ,  Saurabh Sharma

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.

公开(公告)号：US20190102860A1

公开(公告)日：2019-04-04

申请号：US15720385

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Altug Koker ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/0811 ,  H04W52/02 ,  G06T1/20

Abstract: Methods and apparatus relating to tile-aware sector cache for graphics are described. One embodiment enables a sector cache implementation (e.g., in graphics implementations) to reduce the size of the tag space. The reduction in tag space, in turn, reduces power consumption, (e.g., via reduced ways). Moreover, cache efficiency is maintained by keeping the sector utilization at a high rate in one or more embodiments. Other embodiments are also disclosed and claimed.