公开(公告)号：US20190138490A1

公开(公告)日：2019-05-09

申请号：US16040977

申请日：2018-07-20

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/42 ,  G06F13/16 ,  G06F1/324 ,  G06F13/364

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

公开(公告)号：US10284199B2

公开(公告)日：2019-05-07

申请号：US15722985

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  G06F13/40

Abstract: Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.

公开(公告)号：US20190087377A1

公开(公告)日：2019-03-21

申请号：US15706913

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Kenneth P. Foust

IPC: G06F13/42 ,  G06F13/40 ,  G06F21/62 ,  G06F21/85

Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

公开(公告)号：US20190052539A1

公开(公告)日：2019-02-14

申请号：US16021404

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Amit Kumar Srivastava

IPC: H04L12/24 ,  G06F13/40

Abstract: Embodiments include apparatuses, methods, and systems for testing that include a programmable tester coupled to a master-slave device network having a master device and at least one slave device. The programmable tester is to receive a configuration mode from a host to test a function of a selected device of the master device or the at least one slave device. The configuration mode is to indicate that the programmable tester is to be configured to operate in a slave mode or in a master mode. The programmable tester is further configured according to the configuration mode, to send test data to test the function of the selected device, determine a test result based on response data by the selected device to the test data, and indicate whether the selected device is in a faulty state with respect to the function. Other embodiments may also be described and claimed.

公开(公告)号：US20190042495A1

公开(公告)日：2019-02-07

申请号：US15898909

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/06

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

公开(公告)号：US20190028107A1

公开(公告)日：2019-01-24

申请号：US16140355

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava

IPC: H03L7/087 ,  H03L7/23 ,  H03L7/197 ,  H03M1/50

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

公开(公告)号：US20190007054A1

公开(公告)日：2019-01-03

申请号：US16006686

申请日：2018-06-12

Applicant: Intel Corporation

Inventor： Chenchu Punnarao Bandi ,  Amit Kumar Srivastava ,  Navindra Navaratnam

IPC: H03L7/081 ,  G06F1/10

CPC classification number: H03L7/00 ,  G06F1/10 ,  G06F1/12 ,  H03K3/84 ,  H03L7/0812 ,  H03L7/0818

Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.

公开(公告)号：US10083147B2

公开(公告)日：2018-09-25

申请号：US15396376

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/28 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/287 ,  G06F13/387 ,  G06F2213/0026 ,  G06F2213/4002 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

公开(公告)号：US20160285757A1

公开(公告)日：2016-09-29

申请号：US14670213

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Teong Guan Yew

IPC: H04L12/721 ,  H04L12/10

CPC classification number: H04L45/566 ,  H04L12/10 ,  H04L49/109

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

Abstract translation: 第一集成电路的端口耦合到第一通信路径。 配置信息通过端口和第一通信路径在连接到第二设备的连接器和第二集成电路之间传送。 该端口与第一通信路径分离。 端口耦合到第二通信路径。 数据通过端口和第二通信路径在连接器和第二集成电路之间传送。

公开(公告)号：US20150227489A1

公开(公告)日：2015-08-13

申请号：US14457594

申请日：2014-08-12

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Jia Jun Lee ,  Amit Kumar Srivastava ,  Teong Guan T.G. Yew ,  Tim McKee

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/385

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 该方法包括在一对嵌入式高速串行接口数据线中的每一个上发出单端（SE1）信号，指示寄存器访问协议（RAP）消息的SE1跟随SE1信号。 该方法还包括基于RAP消息访问嵌入式高速串行接口组件的寄存器。