公开(公告)号：US11156815B2

公开(公告)日：2021-10-26

申请号：US16336607

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Anna M. Prakash ,  Amanuel M Abebaw ,  Olga Gorbounova ,  Ching-Ping Janet Shen ,  Shan Zhong ,  Mark Saltas

IPC: G02B19/00 ,  G01J1/04

Abstract: Various embodiments disclosed relate to an assembly. The assembly includes a compound parabolic concentrator including an exit aperture that has a generally circular perimeter, which defines a circumference of the exit aperture. The assembly further includes a photodiode sensor generally that is aligned with the exit aperture of the compound parabolic concentrator. An optical adhesive layer adheres the exit aperture of the compound parabolic concentrator to the photodiode sensor. A protrusion extends between at least a portion of the perimeter of the compound parabolic concentrator exit aperture and the photodiode.

公开(公告)号：US20200051894A1

公开(公告)日：2020-02-13

申请号：US16100406

申请日：2018-08-10

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Je-Young Chang ,  Chia-Pin Chiu ,  Shankar Devasenathipathy ,  Betsegaw Kebede Gebrehiwot ,  Chandra Mohan Jha

IPC: H01L23/427 ,  H01L25/18

Abstract: Disclosed herein are thermal assemblies for multi-chip packages (MCPs), as well as related methods and devices. For example, in some embodiments, a thermal assembly for an MCP may include a heat pipe having a ring shape.

公开(公告)号：US20190139926A1

公开(公告)日：2019-05-09

申请号：US16239670

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20180182712A1

公开(公告)日：2018-06-28

申请号：US15390809

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kyle Yazzie

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/83122 ,  H01L2224/83132

Abstract: Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of fiducials to increase recognition of each of the one or more fiducials that includes the fluid by one or more pattern recognition devices. In an example, the fluid is an epoxy and the fiducials are used to determine a placement of components in a component space.

公开(公告)号：US20180145047A1

公开(公告)日：2018-05-24

申请号：US15873567

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US09929119B2

公开(公告)日：2018-03-27

申请号：US15255351

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20170287831A1

公开(公告)日：2017-10-05

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US09666549B2

公开(公告)日：2017-05-30

申请号：US14879418

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaorong Xiong ,  Linda Zhang ,  Robert Nickerson ,  Charles Gealer

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1815 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.

公开(公告)号：US20160293578A1

公开(公告)日：2016-10-06

申请号：US14655688

申请日：2014-07-28

Applicant: INTEL CORPORATION

Inventor： Chuan Hu ,  Chia-Pin Chiu ,  Johanna Swan

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The multiple die have wide pads to facilitate on wafer testing of the multiple die. The wide pads are spaced a minimum distance permitted by a manufacturing process used to manufacture their respective die. The build-up layer above the wide pads is removed. The apparatus also includes metallization on a top side of the build-up layer that substantially fills regions above the wide pads. The metallization includes lands above the wide pads and multiple wires between the wide pads.

Abstract translation: 描述了具有堆积层的装置。 堆积层具有压入堆积层的底侧的多个模的垫侧。 多个管芯具有宽焊盘，以便于在多个管芯的晶片测试上。 宽焊盘间隔开制造用于其相应管芯的制造工艺允许的最小距离。 去除宽垫上方的堆积层。 该装置还包括在积层的顶侧上的金属化，其基本上填充宽焊盘上方的区域。 金属化包括宽焊盘上方的焊盘和宽焊盘之间的多条焊丝。

公开(公告)号：US09437569B2

公开(公告)日：2016-09-06

申请号：US14922425

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.