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公开(公告)号:US20190073514A1
公开(公告)日:2019-03-07
申请号:US16181921
申请日:2018-11-06
Applicant: Intel Corporation
Inventor: Radhakrishnan Venkataraman , James M. Holland , Sayan Lahiri , Pattabhiraman K , Kamal Sinha , Chandrasekaran Sakthivel , Daniel Pohl , Vivek Tiwari , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle , Devan Burke
Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.
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公开(公告)号:US20180308285A1
公开(公告)日:2018-10-25
申请号:US15494696
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Peter L. Doyle , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu , Joydeep Ray , Elmoustapha Ould-Ahmed-Vall , Philip R. Laws , Altug Koker
CPC classification number: G06T17/20 , G06T15/005 , G06T15/04 , G06T15/80 , G06T17/10 , G06T17/205
Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.
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公开(公告)号:US20180300903A1
公开(公告)日:2018-10-18
申请号:US15489068
申请日:2017-04-17
Applicant: Intel Corporation
Inventor: John G. Gierach , Hugues Labbe , Tomer Bar-On , Adam T. Lake , Kai Xiao , Ankur N. Shah , Philip R. Laws , Devan Burke , Abhishek R. Appu , Peter L. Doyle , Elmoustapha Ould-Ahmed-Vall , Travis T. Schluessler , Altug Koker
Abstract: Systems, apparatuses, and methods may provide for technology to render and compress stereoscopic graphical data. In one example, the technology identifies, from graphical data associated with a stereoscopic image defined by a first perspective view and a second perspective view, a background region and a foreground region of a graphical scene in the stereoscopic image, renders graphical data of the identified background region for the first perspective view, and compresses the rendered graphical data.
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公开(公告)号:US12061831B2
公开(公告)日:2024-08-13
申请号:US18474361
申请日:2023-09-26
Applicant: Intel Corporation
Inventor: Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G09G5/391 , G06F3/01 , G06F3/0484 , G06F3/14 , G09G5/00
CPC classification number: G06F3/1438 , G06F3/013 , G06F3/0484 , G09G5/391 , G09G5/001 , G09G2340/0435 , G09G2352/00 , G09G2354/00 , G09G2360/08 , G09G2360/121
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号:US12014701B2
公开(公告)日:2024-06-18
申请号:US18179067
申请日:2023-03-06
Applicant: Intel Corporation
Inventor: Louis Feng , Altug Koker , Tomasz Janczak , Andrew T. Lauritzen , David M. Cimini , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , Philip R. Laws , Devan Burke , Elmoustapha Ould-Ahmed-Vall , Abhishek R. Appu
CPC classification number: G09G5/005 , G06T1/20 , G09G5/001 , G09G5/363 , G09G5/38 , G09G5/391 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/125
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
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公开(公告)号:US11816384B2
公开(公告)日:2023-11-14
申请号:US17959374
申请日:2022-10-04
Applicant: Intel Corporation
Inventor: Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Sanjeev S. Jahagirdar , Balaji Vembu , Devan Burke , Philip R. Laws , Kamal Sinha , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Peter L. Doyle , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Altug Koker
IPC: G06F3/14 , G06F3/01 , G09G5/391 , G06F3/0484 , G09G5/00
CPC classification number: G06F3/1438 , G06F3/013 , G06F3/0484 , G09G5/391 , G09G5/001 , G09G2340/0435 , G09G2352/00 , G09G2354/00 , G09G2360/08 , G09G2360/121
Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.
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公开(公告)号:US11688366B2
公开(公告)日:2023-06-27
申请号:US17461228
申请日:2021-08-30
Applicant: Intel Corporation
Inventor: Travis Schluessler , Abhishek Venkatesh , John Gierach , Tomer Bar-On , Devan Burke
IPC: G06T15/40 , G09G5/36 , G09G5/391 , G06T15/20 , G06T7/70 , G06T15/00 , G09G3/00 , G06T1/20 , G09G5/00 , G06T3/00 , G09G5/397 , G06T1/60 , G09G5/377 , G06F3/14
CPC classification number: G09G5/363 , G06T1/20 , G06T7/70 , G06T15/005 , G06T15/20 , G06T15/405 , G09G3/003 , G09G5/001 , G09G5/391 , G06F3/1446 , G06T1/60 , G06T3/0093 , G06T2210/08 , G06T2210/36 , G06T2210/52 , G09G5/377 , G09G5/397 , G09G2300/026 , G09G2320/0252 , G09G2330/023 , G09G2340/0407 , G09G2340/0428 , G09G2352/00 , G09G2354/00 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/122
Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.
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公开(公告)号:US11593910B2
公开(公告)日:2023-02-28
申请号:US17741934
申请日:2022-05-11
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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公开(公告)号:US11562461B2
公开(公告)日:2023-01-24
申请号:US17529862
申请日:2021-11-18
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
IPC: G06T1/20 , G06T15/80 , G06F3/14 , G06T1/60 , G09G5/36 , G06F3/06 , G06N3/08 , G06N3/04 , G06N3/063 , G09G5/00
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.
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公开(公告)号:US11537403B2
公开(公告)日:2022-12-27
申请号:US17213453
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
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