公开(公告)号：US20230317562A1

公开(公告)日：2023-10-05

申请号：US17708968

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Jan Proschwitz ,  Stefan Reif ,  Vishnu Prasad ,  Georg Seidemann

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/03 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/06515 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0231

Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.

公开(公告)号：US11456116B2

公开(公告)日：2022-09-27

申请号：US16474015

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Bernd Waidhas ,  Sonja Koller ,  Reinhard Mahnkopf ,  Georg Seidemann

IPC: H01F27/24 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02

Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

公开(公告)号：US11239199B2

公开(公告)日：2022-02-01

申请号：US15774906

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US11134573B2

公开(公告)日：2021-09-28

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-grid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US11127813B2

公开(公告)日：2021-09-21

申请号：US16617548

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin

IPC: H01L23/00 ,  H01L21/00 ,  H01L49/02 ,  H01F17/04 ,  H01L21/02 ,  H01L21/56 ,  H01L23/64

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US20200352035A1

公开(公告)日：2020-11-05

申请号：US16642801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Sonja Koller ,  Bernd Waidhas

IPC: H05K3/34 ,  H01L23/498

Abstract: A printed wiring-board island relieves added complexity to a printed circuit board. The printed wiring-board island creates an island form factor in the printed circuit board. Coupling of a semiconductive device package to the printed wiring-board island includes a ball-rid array. The ball-grid array can at least partially penetrate the printed wiring-board island.

公开(公告)号：US20160358848A1

公开(公告)日：2016-12-08

申请号：US15117716

申请日：2014-03-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract translation: 一种微电子封装，包括设置在封装主体内的无源微电子器件，其中所述封装体是所述微电子封装的对所述微电子封装提供支撑和/或刚度的部分。 在倒装芯片型微电子封装中，封装主体可以包括微电子衬底，活性微电子器件电连接到微电子衬底。 在嵌入式设备型微电子封装中，封装体可以包括其中嵌入有源微电子器件的材料。

公开(公告)号：US20160247785A1

公开(公告)日：2016-08-25

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09299672B2

公开(公告)日：2016-03-29

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

公开(公告)号：US12243828B2

公开(公告)日：2025-03-04

申请号：US17355770

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.