公开(公告)号：US20180005349A1

公开(公告)日：2018-01-04

申请号：US15201497

申请日：2016-07-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Sandeep S. Sodhi ,  Joydeep Ray ,  James A. Valerio

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/00

CPC classification number: G06T1/60 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/122

Abstract: Methods and apparatus relating to buffering graphics tiled resource translations in a data port controller TLB (Translation Lookaside Buffer) are described. In an embodiment, controller logic causes storage of information corresponding to a tiled resource in a first entry of a Translation Lookaside Buffer (TLB) in response to a request corresponding to the tiled resource. A second entry of the TLB is capable of storing data corresponding to a coherent memory request. The tiled resource comprise data corresponding to a portion of an image. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240362741A1

公开(公告)日：2024-10-31

申请号：US18662337

申请日：2024-05-13

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/5011 ,  Y02D10/00

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.

公开(公告)号：US11995737B2

公开(公告)日：2024-05-28

申请号：US17527689

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/5011 ,  Y02D10/00

Abstract: Thread dispatch circuitry is configured to dispatch threads of a two-dimensional (2D) thread group based on data access locality associated with the threads. The thread dispatch circuitry can dispatch a first 2D sub-group of the 2D thread group to a compute block of the multiple compute blocks, the first 2D sub-group associated with a first 2D tile of memory and dispatch a second 2D sub-group of the 2D thread group to the compute block of the multiple compute blocks, the second 2D sub-group associated with a second 2D tile of memory.

公开(公告)号：US11436695B2

公开(公告)日：2022-09-06

申请号：US17200581

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20220156875A1

公开(公告)日：2022-05-19

申请号：US17527689

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50

Abstract: Thread dispatch circuitry is configured to dispatch threads of a two-dimensional (2D) thread group based on data access locality associated with the threads. The thread dispatch circuitry can dispatch a first 2D sub-group of the 2D thread group to a compute block of the multiple compute blocks, the first 2D sub-group associated with a first 2D tile of memory and dispatch a second 2D sub-group of the 2D thread group to the compute block of the multiple compute blocks, the second 2D sub-group associated with a second 2D tile of memory.

公开(公告)号：US20210272231A1

公开(公告)日：2021-09-02

申请号：US17200581

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US20210149724A1

公开(公告)日：2021-05-20

申请号：US17103626

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06F9/48 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

公开(公告)号：US20190304052A1

公开(公告)日：2019-10-03

申请号：US16441499

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  David Puffer ,  Abhishek R. Appu ,  Stephen Junkins

IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：US10310895B2

公开(公告)日：2019-06-04

申请号：US15493670

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06F9/00 ,  G06T1/00 ,  G06F9/48 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

公开(公告)号：US20180307606A1

公开(公告)日：2018-10-25

申请号：US15493404

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  James A. Valerio ,  Prasoonkumar Surti

IPC: G06F12/0844 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F12/0844 ,  G06F2212/1016 ,  G06F2212/455 ,  G06T1/20 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.