公开(公告)号：US11670044B2

公开(公告)日：2023-06-06

申请号：US17723328

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

公开(公告)号：US11670041B2

公开(公告)日：2023-06-06

申请号：US17466512

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T15/50 ,  G06T1/60 ,  G06T11/20 ,  G06T15/80 ,  G06T3/40 ,  G06T11/40

CPC classification number: G06T15/503 ,  G06T1/60 ,  G06T11/203 ,  G06T11/40 ,  G06T15/80 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide for technology that selects an anti-aliasing mode for a vertex of a primitive based on a parameter associated with the vertex and generates a coverage mask based on the selected anti-aliasing mode. Additionally, one or more pixels corresponding to the vertex may be shaded based at least partly on the coverage mask, wherein the selected anti-aliasing mode varies across a plurality of vertices in the primitive.

公开(公告)号：US11663774B2

公开(公告)日：2023-05-30

申请号：US17684686

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

CPC classification number: G06T15/503 ,  G06T15/005 ,  G06T15/80 ,  G06T17/205 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US11650928B2

公开(公告)日：2023-05-16

申请号：US17715734

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0895 ,  G06F12/126 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06F12/0895 ,  G06F12/023 ,  G06F12/126 ,  G06T1/60 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/608

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

公开(公告)号：US20230101654A1

公开(公告)日：2023-03-30

申请号：US17484955

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carlos Nava Rodriguez ,  Yoav Harel ,  Joydeep Ray ,  Abhishek R. Appu ,  Vamsee Vardhan Chivukula ,  Benjamin R. Pletcher

IPC: G06T15/00 ,  G06T1/20 ,  G06F13/16

Abstract: Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load to a destination, wherein the destination may be either the texture sampler or the data port; wherein the message router includes arbitration circuitry to select the destination for the texture load, the arbitration circuitry to base selection of the destination at least in part on support by the data port for a format of a memory surface for the texture load; and a utilization metric for the data port representing availability of the data port.

公开(公告)号：US20230061331A1

公开(公告)日：2023-03-02

申请号：US17960611

申请日：2022-10-05

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06F7/483 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063 ,  G06F9/50 ,  G06F9/38 ,  G06N20/00

Abstract: One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

公开(公告)号：US11586548B2

公开(公告)日：2023-02-21

申请号：US17191473

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US11521294B2

公开(公告)日：2022-12-06

申请号：US17036950

申请日：2020-09-29

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Abhishek R. Appu ,  Balaji Vembu

IPC: G06T1/60 ,  G06T1/20

Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.

公开(公告)号：US11520723B2

公开(公告)日：2022-12-06

申请号：US17367169

申请日：2021-07-02

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C. Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US11520555B2

公开(公告)日：2022-12-06

申请号：US17162864

申请日：2021-01-29

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  G06F3/147 ,  G06T1/20 ,  G09G5/36 ,  H04L65/402 ,  G09G3/00 ,  H04L67/131

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.