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    Vector processor supporting linear interpolation on multiple dimensions
    43.
    发明授权
    Vector processor supporting linear interpolation on multiple dimensions 有权

    公开(公告)号：US12106101B2

    公开(公告)日：2024-10-01

    申请号：US17131939

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Joseph Williams ,  Zoran Zivkovic

    IPC: G06F9/30 ,  G06F9/38 ,  G06F16/901

    CPC classification number: G06F9/30036 ,  G06F9/3812 ,  G06F9/3873 ,  G06F16/9017

    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

    HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    46.
    发明公开
    HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE 审中-公开

    公开(公告)号：US20230205730A1

    公开(公告)日：2023-06-29

    申请号：US17560637

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

    IPC: G06F15/80 ,  G06F17/11

    CPC classification number: G06F15/8092 ,  G06F17/11

    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

    DIGITAL PRE-DISTORTION (DPD) ADAPTATION USING A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    47.
    发明公开
    DIGITAL PRE-DISTORTION (DPD) ADAPTATION USING A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE 审中-公开

    公开(公告)号：US20230205727A1

    公开(公告)日：2023-06-29

    申请号：US17560685

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

    IPC: G06F15/80 ,  G06F1/26

    CPC classification number: G06F15/80 ,  G06F1/26

    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    48.
    发明申请
    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD 有权

    公开(公告)号：US20220197641A1

    公开(公告)日：2022-06-23

    申请号：US17131970

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Jeroen Leijten ,  Joseph Williams

    IPC: G06F9/30 ,  G06F9/46 ,  G06F9/54 ,  G06F9/38

    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

    Time-interleaved analog-to-digital converter system
    49.
    发明授权
    Time-interleaved analog-to-digital converter system 有权

    公开(公告)号：US11271578B2

    公开(公告)日：2022-03-08

    申请号：US17059495

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Matteo Camponeschi ,  Jose Luis Ceballos ,  Christian Lindholm

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/10

    Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

    Digital-to-analog converter, transmitter, base station and mobile device
    50.
    发明授权
    Digital-to-analog converter, transmitter, base station and mobile device 有权

    公开(公告)号：US10938404B1

    公开(公告)日：2021-03-02

    申请号：US16728163

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Ramon Sanchez ,  Kameran Azadet ,  Martin Clara ,  Daniel Gruber

    IPC: H03M1/66 ,  H03K3/84 ,  G06F7/58 ,  H04B1/40 ,  H04W88/08

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code. The digital-to-analog converter comprises a cell activation circuit configured to selectively activate one or more of the plurality of digital-to-analog converter cells based on the modified second digital control code. Each activated digital-to-analog converter cell is configured to output a respective cell output signal. Further, the digital-to-analog converter comprises an output configured to output an analog output signal based on the cell output signals.

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