公开(公告)号：US10334041B2

公开(公告)日：2019-06-25

申请号：US14949265

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi ,  Namakkal N. Venkatesan ,  Roger Keith Wiles

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/26 ,  H04L29/06

Abstract: A network interface device (NID) interfaced with a host machine communicates with a local link of the host machine to obtain transaction-specific data relied upon by the host machine to be delivered to a destination by the NID according to a reliable message delivery protocol. The NID conducts communications over a network in response to obtaining of the transaction-specific data, with the network communications including execution of the reliable message delivery protocol independent of any operability of the host machine.

公开(公告)号：US10318291B2

公开(公告)日：2019-06-11

申请号：US15585505

申请日：2017-05-03

Applicant: INTEL CORPORATION

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Charles R. Yount ,  Suleyman Sair ,  Kshitij A. Doshi

IPC: G06F9/30 ,  G06F7/06

Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.

公开(公告)号：US20180285288A1

公开(公告)日：2018-10-04

申请号：US15475216

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Kshitij A. Doshi ,  Mark A. Schmisseur

IPC: G06F13/16 ,  G06F12/0831 ,  H04L12/861 ,  G06F12/1018

Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

公开(公告)号：US10067870B2

公开(公告)日：2018-09-04

申请号：US15088985

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F13/00 ,  G06F13/28

Abstract: An apparatus and method are described for low overhead synchronous page table updates. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a translation lookaside buffer (TLB) comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; locking circuitry to allow a thread to lock a first page table entry (PTE) in the TLB to ensure that only one thread can modify the first PTE at a time, wherein the TLB is to modify the first PTE upon the thread acquiring the lock; a PTE invalidation circuit to execute a PTE invalidate instruction on a first core to invalidate the first PTE in other TLBs of other cores, the PTE invalidation circuit, responsive to execution of the PTE invalidate instruction, to responsively determine a number of other TLBs of other cores which need to be notified of the PTE invalidation, transmit PTE invalidate messages to the other TLBs, and wait for responses; and the locking circuitry to release the lock on the first PTE responsive to receiving responses from all of the other TLBs.

公开(公告)号：US09910669B2

公开(公告)日：2018-03-06

申请号：US14752014

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F9/312 ,  G06F9/44 ,  G06F9/30 ,  G06F12/1027

CPC classification number: G06F9/30029 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/3836 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2201/885 ,  G06F2212/452 ,  G06F2212/68

Abstract: A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit to retire the first instruction. The core includes logic to execute the first instruction, including logic to repeatedly record a translation lookaside buffer (TLB) until a designated number of records are determined, and flush the TLB after a flush interval.

公开(公告)号：US20180056935A1

公开(公告)日：2018-03-01

申请号：US15641090

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  George J. Chaltas

IPC: B60R22/48 ,  B60N2/26 ,  B60N2/00 ,  B60N2/28

CPC classification number: B60R22/48 ,  B60N2/002 ,  B60N2/26 ,  B60N2002/2815 ,  B60R2022/4816 ,  B60R2022/4858 ,  G08B21/02 ,  G08B21/22 ,  G08B23/00 ,  G08B25/10

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with providing alerts to a caregiver in a vehicle. In various embodiments, an apparatus may include a first sensor coupled with a restraint to provide a restraint indicator, a second sensor coupled with a securing component to provide an attachment indicator, and an alert module operated by one or more processors to cause a wireless transmitter to transmit an alert signal based at least in part on the restraint indicator and the attachment indicator. In various embodiments, a warning apparatus may include an output device and a warning module operated by one or more processors to activate the output device based at least in part on a wireless alert signal from a car seat in a vehicle that indicates the car seat is in use.

公开(公告)号：US20170357514A1

公开(公告)日：2017-12-14

申请号：US15687315

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Kshitij A. Doshi ,  Charles R. Yount ,  Suleyman Sair

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/3887 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3836 ,  G06F15/8061

Abstract: Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.

公开(公告)号：US09405706B2

公开(公告)日：2016-08-02

申请号：US14496255

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Karthik Raman ,  Christopher J. Hughes

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/126 ,  G06F9/30047 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3889 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

Abstract translation: 处理器包括前端，高速缓存和高速缓存控制器。 前端包括接收定义优先级数据集的指令的逻辑。 优先级数据集包括各自对应于相应优先级的存储器地址范围。 高速缓存控制器包括用于检测所请求的高速缓存值的高速缓存中的未命中的逻辑，从高速缓存确定候选高速缓存受害者，根据优先级数据确定所请求的高速缓存值和候选高速缓存受害者的优先级， 基于所述候选高速缓存牺牲者的优先级小于或等于所请求的高速缓存值的优先级的确定来确定缓存受害者。

公开(公告)号：US20160092373A1

公开(公告)日：2016-03-31

申请号：US14496255

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Karthik Raman ,  Christopher J. Hughes

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/126 ,  G06F9/30047 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3889 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

Abstract translation: 处理器包括前端，高速缓存和高速缓存控制器。 前端包括接收定义优先级数据集的指令的逻辑。 优先级数据集包括各自对应于相应优先级的存储器地址范围。 高速缓存控制器包括用于检测所请求的高速缓存值的高速缓存中的未命中的逻辑，从高速缓存确定候选高速缓存受害者，根据优先级数据确定所请求的高速缓存值和候选高速缓存受害者的优先级， 基于所述候选高速缓存牺牲者的优先级小于或等于所请求的高速缓存值的优先级的确定来确定缓存受害者。

公开(公告)号：US20250153712A1

公开(公告)日：2025-05-15

申请号：US18956235

申请日：2024-11-22

Applicant: Intel Corporation

Inventor： David Gomez Gutierrez ,  Javier Felip Leon ,  Kshitij A. Doshi ,  Leobardo E. Campos Macias ,  Nilesh Amar Ahuja ,  Omesh Tickoo

IPC: B60W30/095 ,  B60W50/14 ,  G06V10/62 ,  G06V10/82 ,  G06V20/58 ,  G06V40/10

Abstract: An apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.