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    Leveraging control surface fast clears to optimize 3D operations
    42.
    发明授权
    Leveraging control surface fast clears to optimize 3D operations 有权

    公开(公告)号：US10964087B2

    公开(公告)日：2021-03-30

    申请号：US16546658

    申请日：2019-08-21

    Applicant: Intel Corporation

    Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

    IPC: G06T15/04 ,  G06T15/00 ,  G06T15/80

    Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.

    Tile-based multiple resolution rendering of images
    43.
    发明授权
    Tile-based multiple resolution rendering of images 有权

    公开(公告)号：US10937126B2

    公开(公告)日：2021-03-02

    申请号：US15982680

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T3/40 ,  G06T1/20

    Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.

    Method and apparatus for subdividing shader workloads in a graphics processor for efficient machine configuration
    46.
    发明授权
    Method and apparatus for subdividing shader workloads in a graphics processor for efficient machine configuration 有权

    公开(公告)号：US10360717B1

    公开(公告)日：2019-07-23

    申请号：US15858396

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： John G. Gierach ,  Travis Schluessler ,  Thomas F. Raoux ,  Peng Guo

    IPC: G06F9/38 ,  G06T1/20 ,  G06T15/00

    Abstract: An apparatus and method for splitting shaders. For example, one embodiment of a method comprises: receiving a request for compilation of a shader in a graphics processing environment; determining whether there is sufficient work associated with the shader to justify splitting the shader into two or more blocks of program code; evaluating the program code of the shader to identify dependencies between the blocks of program code if there is sufficient work; subdividing the shader into the two or more blocks in accordance with the identified dependencies; and individually executing the two or more blocks of code on a graphics processor. In addition, one embodiment includes the operations of determining whether any of the regions that can be subdivided are likely to run faster with different machine configurations than if the shader is executed without being subdivided, and subdividing the shader only for those regions that are likely to run faster with different machine configurations.

    System and method for adapting executable object to a processing unit
    50.
    发明授权
    System and method for adapting executable object to a processing unit 有权

    公开(公告)号：US11550600B2

    公开(公告)日：2023-01-10

    申请号：US17090295

    申请日：2020-11-05

    Applicant: Intel Corporation

    Inventor： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

    IPC: G06F9/448 ,  G06F16/215 ,  G06T1/60 ,  G06T1/20

    Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

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