中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

82 records (took 0.037 seconds)

    PASID based routing extension for scalable IOV systems
    44.
    发明授权
    PASID based routing extension for scalable IOV systems 有权

    公开(公告)号：US12086082B2

    公开(公告)日：2024-09-10

    申请号：US17026516

    申请日：2020-09-21

    Applicant: Intel Corporation

    Inventor： Pratik Marolia ,  Sanjay Kumar ,  Rajesh Sankaran ,  Utkarsh Y. Kakaiya

    IPC: G06F13/20 ,  G06F3/06 ,  G06F9/455

    CPC classification number: G06F13/20 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0662 ,  G06F3/0679 ,  G06F9/45558

    Abstract: Methods and apparatus for PASID-based routing extension for Scalable IOV systems. The system may include a Central Processing Unit (CPU) operatively coupled to a scalable Input/Output Virtualization (IOV) device via an in-line device such as a smart controller or accelerator. A Control Process Address Space Identifier (C-PASID) associated with a first memory space is implemented in an Assignable Device Interface (ADI) for the IOV device. The ADI also implements a Data PASID (D-PASID) associated with a second memory space in which data are stored. The C-PASID is used to fetch a descriptor in the first memory space and the D-PASID is employed to fetch data in the second memory space. A hub embedded on the in-line device or implemented as a discrete device is used to steer memory access requests and/or fetches to the CPU or to the in-line device using the C-PASID and D-PASID. IOV devices include multi-PASID helper devices and off-the-shelf devices such as NICs with modified ADIs to support C-PASID and D-PASID usage.

    Techniques for virtual machine transfer and resource management
    46.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11995462B2

    公开(公告)日：2024-05-28

    申请号：US18153177

    申请日：2023-01-11

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES
    50.
    发明申请
    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES 有权

    公开(公告)号：US20230103000A1

    公开(公告)日：2023-03-30

    申请号：US17485386

    申请日：2021-09-25

    Applicant: Intel Corporation

    Inventor： Rupin Vakharwala ,  Prashant Sethi ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  David J. Harriman ,  Utkarsh Y. Kakaiya ,  Vinay Raghav ,  Ashok Raj ,  Siva Bhanu Krishna Boga

    IPC: G06F12/1027 ,  G06F12/0802 ,  G06F13/42

    Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer. The second interconnect is in the only path between the device and the system memory.

Patent Agency Ranking