Abstract:
The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
Abstract:
The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.