公开(公告)号：US20230089099A1

公开(公告)日：2023-03-23

申请号：US18071692

申请日：2022-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roman Nudelman ,  Gil Bloch ,  Daniel Marcovitch

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/54

Abstract: A processing device includes an interface and one or more processing circuits. The interface is to connect to a host processor. The one or more processing circuits are to receive from the host processor, via the interface, a notification specifying an operation for execution by the processing device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks, in response to the notification, to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation in accordance with the schedule.

公开(公告)号：US20220078043A1

公开(公告)日：2022-03-10

申请号：US17013677

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US20250165402A1

公开(公告)日：2025-05-22

申请号：US18513563

申请日：2023-11-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Ran Avraham Koren ,  Daniel Marcovitch ,  Gal Shalom ,  Ariel Shahar

IPC: G06F12/0862 ,  G06F12/0831 ,  G06F13/16

Abstract: A system includes a processing device and a peripheral device. The processing device is to assign a memory region in a memory. The peripheral device is to set a memory-access policy responsively to usage characteristics of the memory region, and to access data in the memory region using Direct Memory Access (DMA) in accordance with the memory-access policy.

公开(公告)号：US12277068B2

公开(公告)日：2025-04-15

申请号：US18299732

申请日：2023-04-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Shalom ,  Daniel Marcovitch ,  Ran Avraham Koren ,  Amir Sharaffy ,  Shay Aisman ,  Ariel Shahar

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/1027

Abstract: A peripheral device includes a bus interface and an Address Translation Service (ATS) controller. The bus interface is to communicate over a peripheral bus. The ATS controller is to communicate over the peripheral bus, including sending address translation requests and receiving address translations in response to the address translation requests, to cache at least some of the address translations in one or more Address Translation Caches (ATCs), to estimate one or more statistical properties of the received address translations, and to configure the one or more ATCs based on the one or more statistical properties.

公开(公告)号：US12229072B2

公开(公告)日：2025-02-18

申请号：US18598382

申请日：2024-03-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Dotan David Levi ,  Eyal Srebro ,  Eliel Peretz ,  Roee Moyal ,  Richard Graham ,  Gil Bloch ,  Sean Pieper

IPC: G06F13/42 ,  G06F7/76

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

公开(公告)号：US12174765B2

公开(公告)日：2024-12-24

申请号：US17707555

申请日：2022-03-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

公开(公告)号：US20240143527A1

公开(公告)日：2024-05-02

申请号：US17977910

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Roman Nudelman ,  Noam Bloch

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1668 ,  G06F2213/0026 ,  G06F2213/3808

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

公开(公告)号：US20230409327A1

公开(公告)日：2023-12-21

申请号：US17844461

申请日：2022-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Eliel Peretz ,  Richard Graham ,  Daniel Marcovitch ,  Gil Bloch ,  Roee Moyal ,  Eyal Srebro ,  Sean Midthun Pieper

IPC: G06F9/30 ,  G06F9/445

CPC classification number: G06F9/30192 ,  G06F9/30025 ,  G06F9/44542

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include circuitry that collects data received from a data source, references a descriptor that describes a data reformat operation to perform on the data received from the data source, reformats the data received from the data source according to the data reformat operation, and provides the reformatted data to the data target via the second device interface.

公开(公告)号：US20230353419A1

公开(公告)日：2023-11-02

申请号：US18349148

申请日：2023-07-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US11785087B1

公开(公告)日：2023-10-10

申请号：US17977905

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Richard Graham

IPC: H04L67/1097 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L67/1097 ,  G06F13/4265 ,  G06F15/17331

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.