公开(公告)号：US11328782B2

公开(公告)日：2022-05-10

申请号：US17247266

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ke Liang ,  Jun Xu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.

公开(公告)号：US20220139465A1

公开(公告)日：2022-05-05

申请号：US17087738

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34 ,  H03K19/17728

Abstract: Memory might include a controller configured to cause the memory to apply a boost voltage level to each capacitance of a plurality of capacitances each connected to a respective node of a sense circuit, selectively discharge each of the nodes through respective memory cells selected for a sense operation, measure a current demand of the plurality of capacitances while each of the nodes is connected to its respective memory cell, determine a deboost voltage level in response to the measured current demand, apply the deboost voltage level to each capacitance of the plurality of capacitances, and determine a respective data state of each memory cell of the plurality of memory cells while the deboost voltage level is applied to each capacitance of the plurality of capacitances.

公开(公告)号：US11211129B2

公开(公告)日：2021-12-28

申请号：US16054206

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C11/56

Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.

公开(公告)号：US10381085B2

公开(公告)日：2019-08-13

申请号：US15503786

申请日：2016-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C16/16 ,  G11C16/04

Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.

公开(公告)号：US20240404615A1

公开(公告)日：2024-12-05

申请号：US18800670

申请日：2024-08-12

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

Abstract: A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including initiating an erase operation performed with respect to the memory array, identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array, and causing an indication of the at least one defect to be generated. The erase operation includes a select gate scan sub-operation.

公开(公告)号：US11688476B2

公开(公告)日：2023-06-27

申请号：US17568797

申请日：2022-01-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

公开(公告)号：US20230170016A1

公开(公告)日：2023-06-01

申请号：US18096072

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0038

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

公开(公告)号：US20230067457A1

公开(公告)日：2023-03-02

申请号：US17889578

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

公开(公告)号：US20230060943A1

公开(公告)日：2023-03-02

申请号：US17889648

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G06F3/06

Abstract: A system includes a memory device including a memory array and a processing device, operatively coupled with the memory array, to perform operations including causing defect management information to be obtained from the memory device. The defect management information includes status information with respect to a status of the memory array and supplemental defect management information associated with a media access operation performed with respect to the memory array. The operations further include analyzing the defect management information to determine a likelihood of defect with respect to the memory array, and identifying, based on the likelihood of defect, a defect status of the memory array.

公开(公告)号：US11442091B2

公开(公告)日：2022-09-13

申请号：US16877710

申请日：2020-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G11C16/08 ,  G11C16/04 ,  G01R27/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.