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    PROCESSOR AND METHOD OF DETERMINING A NORMALIZATION COUNT
    41.
    发明申请
    PROCESSOR AND METHOD OF DETERMINING A NORMALIZATION COUNT 审中-公开
    处理器和确定标准化计数的方法

    公开(公告)号：WO2009089410A2

    公开(公告)日：2009-07-16

    申请号：PCT/US2009/030537

    申请日：2009-01-09

    Applicant: QUALCOMM Incorporated ,  KRITHIVASAN, Shankar ,  PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao

    Inventor： KRITHIVASAN, Shankar ,  PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao

    IPC: G06F7/483

    CPC classification number: G06F7/74 ,  G06F7/49936

    Abstract: In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.

    Abstract translation: 在特定实施例中，公开了一种方法，其包括接收将在归一化逻辑电路处归一化的操作数，其中操作数包括多个位。 该方法进一步包括当操作数的值等于零时生成零输出，并且当该值不等于零时，生成表示比操作数的前导位的计数小1的数的输出值。

    SYSTEM AND METHOD OF DETERMINING AN ADDRESS OF AN ELEMENT WITHIN A TABLE
    43.
    发明申请
    SYSTEM AND METHOD OF DETERMINING AN ADDRESS OF AN ELEMENT WITHIN A TABLE 审中-公开
    在表中确定元件的地址的系统和方法

    公开(公告)号：WO2009067598A1

    公开(公告)日：2009-05-28

    申请号：PCT/US2008/084189

    申请日：2008-11-20

    Applicant: QUALCOMM Incorporated ,  KRITHIVASAN, Shankar ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich J.

    Inventor： KRITHIVASAN, Shankar ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich J.

    IPC: G06F9/30 ,  G06F9/355 ,  G06F9/315

    CPC classification number: G06F9/3555 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004

    Abstract: In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.

    Abstract translation: 在特定实施例中，公开了一种方法，其包括执行单个指令以识别存储在存储器中的表中的位置。 单个指令可由处理器执行以从第一寄存器提取位字段数据，并将位字段数据插入第二寄存器的索引部分。 第二寄存器包括表地址部分和索引部分。 表地址部分包括标识与表相关联的存储器位置的表地址。 表地址和位字段数据组合起来，形成一个索引地址给表中的一个元素。

    METHOD AND SYSTEM FOR INSTRUCTION STUFFING OPERATIONS DURING NON-INTRUSIVE DIGITAL SIGNAL PROCESSOR DEBUGGING
    45.
    发明申请
    METHOD AND SYSTEM FOR INSTRUCTION STUFFING OPERATIONS DURING NON-INTRUSIVE DIGITAL SIGNAL PROCESSOR DEBUGGING 审中-公开
    非侵入式数字信号处理器调试期间的指令运行操作方法与系统

    公开(公告)号：WO2008061105A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084587

    申请日：2007-11-13

    Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    IPC: G06F11/36

    CPC classification number: G06F11/362 ,  G06F11/3656

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREADED DIGITAL SIGNAL PROCESSOR
    46.
    发明申请
    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREADED DIGITAL SIGNAL PROCESSOR 审中-公开
    多线程数字信号处理器的非侵入性，线性选择，调试方法和系统

    公开(公告)号：WO2008061067A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084456

    申请日：2007-11-12

    Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统提供处理多线程过程中的指令，包括使用断点指令来产生调试事件。 生成调试事件是为了响应断点指令的执行并执行调试指令来响应调试事件。 调试指令通过将至少一个或多个线程转换到调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中执行的调试指令的调试返回。

    METHOD AND SYSTEM TO COMBINE MULTIPLE REGISTER UNITS WITHIN A MICROPROCESSOR
    48.
    发明申请
    METHOD AND SYSTEM TO COMBINE MULTIPLE REGISTER UNITS WITHIN A MICROPROCESSOR 审中-公开
    在微处理器中组合多个寄存器单元的方法和系统

    公开(公告)号：WO2008016902A1

    公开(公告)日：2008-02-07

    申请号：PCT/US2007/074820

    申请日：2007-07-31

    Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

    Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

    IPC: G06F9/315

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30112

    Abstract: A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are further combined during execution of a single instruction to form a resulting register unit. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit from the first register unit and a second half word unit from the second register unit are retrieved. The first half word unit and the second half word unit are further input into corresponding high and low portions of a resulting register unit to form the resulting register unit during execution of a single instruction. Finally, the resulting register unit is stored within the register file structure for further processing.

    Abstract translation: 描述了在微处理器内组合多个寄存器单元的方法和系统，例如数字信号处理器。 从处理单元内的寄存器文件结构检索第一寄存器单元和第二寄存器单元，第一寄存器单元和第二寄存器单元非相邻地位于寄存器堆栈结构内。 在执行单个指令期间，第一寄存器单元和第二寄存器单元进一步组合以形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。 或者，检索来自第一寄存器单元的第一半字单元和来自第二寄存器单元的第二半字单元。 第一半字单元和第二半字单元进一步输入到所得寄存器单元的对应高和低部分，以在单个指令的执行期间形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。

    POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER
    49.
    发明申请
    POINTER COMPUTATION METHOD AND SYSTEM FOR A SCALABLE, PROGRAMMABLE CIRCULAR BUFFER 审中-公开
    指针计算方法和系统，用于可扩展的可编程循环缓冲器

    公开(公告)号：WO2007048133A2

    公开(公告)日：2007-04-26

    申请号：PCT/US2006/060133

    申请日：2006-10-20

    Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ZENG, Mao ,  JAMIL, Sujat ,  ANDERSON, William, C.

    Inventor： PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ZENG, Mao ,  JAMIL, Sujat ,  ANDERSON, William, C.

    IPC: G06F9/355

    CPC classification number: G06F5/10 ,  G06F9/3552 ,  G06F9/3851 ,  G06F2205/106

    Abstract: Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.

    Abstract translation: 用于处理各种应用的数字信号的技术，包括在通信（例如CDMA）系统中。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址以及远离起始地址长度而小于2的幂的结束地址来确定 大于长度。 方法和系统确定循环缓冲区内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，循环缓冲区内的新指针位置，从当前指针位置移位数字 的步幅值。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

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