公开(公告)号：EP3491535A2

公开(公告)日：2019-06-05

申请号：EP17731971.2

申请日：2017-06-02

Applicant: Qualcomm Incorporated

Inventor： MATHEW, Deepak ,  INGLE, Ajay Anant ,  SUN, Yurong ,  ZHU, Jianming ,  HOFFMAN, Marc

IPC: G06F17/17 ,  G06F7/544 ,  G06F9/30

公开(公告)号：EP3033670A1

公开(公告)日：2016-06-22

申请号：EP14759362.8

申请日：2014-08-04

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc Murray ,  MATHEW, Deepak ,  ZENG, Mao

IPC: G06F9/30 ,  G06F9/38

Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.

Abstract translation: 在特定实施例中，一种方法包括在处理器处执行向量指令。 矢量指令包括包括多个元素的矢量输入。 执行向量指令包括提供多个元素中的第一元素作为第一输出。 执行向量指令还包括对第一元素和多个元素的第二元素执行算术运算以提供第二输出。 执行向量指令还包括将第一输出和第二输出存储在输出向量中。

公开(公告)号：EP2635968A1

公开(公告)日：2013-09-11

申请号：EP11784868.9

申请日：2011-11-01

Applicant: Qualcomm Incorporated

Inventor： LIN, Jentsung Ken ,  INGLE, Ajay Anant ,  KUO, Eai-hsin A. ,  BASSETT, Paul Douglas

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30043 ,  G06F9/3857

Abstract: A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.

公开(公告)号：EP2591420A1

公开(公告)日：2013-05-15

申请号：EP11738095.6

申请日：2011-07-05

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay Anant ,  PLONDKE, Erich James ,  RAB, Muhammad T.

IPC: G06F12/10

Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

公开(公告)号：EP2542963A1

公开(公告)日：2013-01-09

申请号：EP11708631.4

申请日：2011-03-02

Applicant: Qualcomm Incorporated

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

公开(公告)号：EP2524315A1

公开(公告)日：2012-11-21

申请号：EP11702535.3

申请日：2011-01-14

Applicant: Qualcomm Incorporated

Inventor： INGLE, Ajay Anant ,  LIN, Jentsung ,  TOLEY, Rahul R.

IPC: G06F13/16

CPC classification number: G06F13/1678

Abstract: A multi-stage multiplexing operation that includes combined selection and data alignment or data replication is disclosed. In a particular embodiment, a method includes performing a first stage of a multi-stage multiplexing operation. During the first stage, a first data source is selected from a first plurality of data sources. At least one of a first data alignment operation and a first data replication operation is also performed on first data from the selected first data source during the first stage.

公开(公告)号：EP2223221A1

公开(公告)日：2010-09-01

申请号：EP08847036.4

申请日：2008-11-07

Applicant: QUALCOMM Incorporated

Inventor： BASSETT, Paul ,  CODRESCU, Lucian ,  INGLE, Ajay Anant ,  PLONDKE, Erich

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

Abstract: The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.

公开(公告)号：EP1943588A2

公开(公告)日：2008-07-16

申请号：EP06846216.7

申请日：2006-11-02

Applicant: QUALCOMM Incorporated

Inventor： AHMED, Muhammad ,  INGLE, Ajay Anant ,  JAMIL, Sujat

IPC: G06F9/355

CPC classification number: G06F9/30181 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.