公开(公告)号：EP4136852A1

公开(公告)日：2023-02-22

申请号：EP21722056.5

申请日：2021-04-07

Applicant: QUALCOMM INCORPORATED

Inventor： RUSANOVSKYY, Dmytro ,  CHEN, Jianle ,  ZHANG, Yan ,  KARCZEWICZ, Marta

IPC: H04N19/91 ,  H04N19/13 ,  H04N19/176 ,  H04N19/60 ,  H04N19/186 ,  H04N19/70

公开(公告)号：EP4136851A1

公开(公告)日：2023-02-22

申请号：EP21724836.8

申请日：2021-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： RUSANOVSKYY, Dmytro ,  ZHANG, Yan ,  KARCZEWICZ, Marta

IPC: H04N19/70 ,  H04N19/82 ,  H04N19/117

公开(公告)号：EP4133727A1

公开(公告)日：2023-02-15

申请号：EP21722700.8

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： RUSANOVSKYY, Dmytro ,  RAMASUBRAMONIAN, Adarsh Krishnan ,  ZHANG, Yan ,  KARCZEWICZ, Marta

IPC: H04N19/186 ,  H04N19/169 ,  H04N19/70 ,  H04N19/85

公开(公告)号：EP3997882A1

公开(公告)日：2022-05-18

申请号：EP20750082.8

申请日：2020-07-10

Applicant: QUALCOMM Incorporated

Inventor： RUSANOVSKYY, Dmytro ,  ZHANG, Yan

IPC: H04N19/52 ,  H04N19/157 ,  H04N19/176

公开(公告)号：EP3449674A1

公开(公告)日：2019-03-06

申请号：EP16899783.1

申请日：2016-04-27

Applicant: Qualcomm Incorporated

Inventor： GUAN, Xuepan ,  SIU, Ta-Yan ,  LIOU, Tim ,  LIU, Haizhou ,  LI, Xiaoyu ,  BAI, Lu ,  ZHANG, Yan ,  LONG, Xiaojian ,  LI, Gaoshan ,  LI, Xiaopeng

IPC: H04W48/18

公开(公告)号：EP2070247A2

公开(公告)日：2009-06-17

申请号：EP07798523.2

申请日：2007-06-13

Applicant: Qualcomm Incorporated

Inventor： SAINT-LAURENT, Martin ,  ZHANG, Yan

IPC: H04L7/02

CPC classification number: H04L7/0083 ,  G06F1/08

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.