公开(公告)号：US07821089B2

公开(公告)日：2010-10-26

申请号：US12204371

申请日：2008-09-04

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L31/113

CPC classification number: H01L27/14683 ,  H01L27/1463

Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

公开(公告)号：US20100167644A1

公开(公告)日：2010-07-01

申请号：US12377627

申请日：2007-08-15

Applicant: Ian Winter ,  Alastair Lefley ,  Robin Wilson

Inventor： Ian Winter ,  Alastair Lefley ,  Robin Wilson

IPC: H04B5/00

CPC classification number: H04B5/02 ,  H04B5/0068

Abstract: A near field RF communicator has: an antenna operable to generate an RF signal to enable inductive coupling via the magnetic field of the RF signal between the antenna and another near field RF communicator or RF transponder in near field range; and a signal generator operable to generate a multi-level digital sine wave drive signal to drive the antenna to generate the RF signal, wherein the signal generator comprises a selector operable to select one or more digital sequences to provide one or more digital signals from which the digital sine wave drive signal is generated.

Abstract translation: 近场RF通信器具有：天线，其可操作以产生RF信号，以通过天线与近场范围内的另一近场RF通信器或RF应答器之间的RF信号的磁场实现电感耦合; 以及信号发生器，其可操作以产生多级数字正弦波驱动信号以驱动所述天线以产生所述RF信号，其中所述信号发生器包括选择器，所述选择器可操作以选择一个或多个数字序列以提供一个或多个数字信号， 产生数字正弦波驱动信号。

公开(公告)号：US07741172B2

公开(公告)日：2010-06-22

申请号：US11463613

申请日：2006-08-10

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/8234

CPC classification number: H01L27/0814 ,  H01L29/868 ,  Y10S438/979 ,  Y10S438/983

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract translation: 正 - 内 - 负（PIN）/负 - 本征 - 正（NIP）二极管包括具有彼此相对的第一和第二主表面的半导体衬底。 半导体衬底具有第一导电性。 PIN / NIP二极管包括形成在第一主表面中的至少一个沟槽，其限定至少一个台面。 沟槽延伸到半导体衬底中的第一深度位置。 PIN / NIP二极管包括靠近第一主表面和沟槽的侧壁和底部的第一阳极/阴极层。 第一阳极/阴极层具有与第一导电性相反的第二导电性。 PIN / NIP二极管包括靠近第二主表面的第二阳极/阴极层，衬在沟槽上的第一钝化材料和衬在台面上的第二钝化材料。 第二阳极/阴极层是第一导电性。

公开(公告)号：USD609285S1

公开(公告)日：2010-02-02

申请号：US29313741

申请日：2009-02-06

Applicant: Robin Wilson ,  Randy Wilson

Designer： Robin Wilson ,  Randy Wilson

公开(公告)号：US07576404B2

公开(公告)日：2009-08-18

申请号：US11609934

申请日：2006-12-13

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L31/062

CPC classification number: H01L31/022408

Abstract: A backlit photodiode array includes a semiconductor substrate having first and second main surfaces opposite to each other. A first dielectric layer is formed on the first main surface. First and second conductive vias are formed extending from the second main surface through the semiconductor substrate and the first dielectric layer. The first and second conductive vias are isolated from the semiconductor substrate by a second dielectric material. A first anode/cathode layer of a first conductivity is formed on the first dielectric layer and is electrically coupled to the first conductive via. An intrinsic semiconductor layer is formed on the first anode/cathode layer. A second anode/cathode layer of a second conductivity opposite to the first conductivity is formed on the intrinsic semiconductor layer and is electrically coupled to the second conductive via.

Abstract translation: 背光光电二极管阵列包括具有彼此相对的第一和第二主表面的半导体衬底。 第一介电层形成在第一主表面上。 第一和第二导电通孔从第二主表面延伸穿过半导体衬底和第一介电层形成。 第一和第二导电通孔通过第二电介质材料与半导体衬底隔离。 在第一电介质层上形成第一导电性的第一阳极/阴极层，并与第一导电通孔电耦合。 在第一阳极/阴极层上形成本征半导体层。 在本征半导体层上形成具有与第一导电性相反的第二导电性的第二阳极/阴极层，并与第二导电通孔电耦合。

公开(公告)号：US20090011706A1

公开(公告)日：2009-01-08

申请号：US12283535

申请日：2008-09-12

Applicant: Robin Wilson ,  David Miles

Inventor： Robin Wilson ,  David Miles

IPC: H04B5/00

CPC classification number: H04B5/02 ,  H04B5/0037 ,  H04B5/0075

Abstract: A near field RF communicator has an inductive coupler (10) to enable inductive coupling with a magnetic field of an RF signal. A demodulator (102) extracts modulation from an inductively coupled magnetic field. A power provider (109) provides a first power supply for the communicator independent of any inductively coupled signal while a power deriver derives a second power supply from an RF signal inductively coupled to the antenna. A regulator (206; 1302) regulates a voltage supplied by at least one of the first and second power supplies on the basis of a comparison with a reference voltage. A modulator (M) is provided to modulate an inductively coupled magnetic field with data to be communicated via the inductive coupling. In an example, a regulator controller is provided to prevent operation of the regulator in the event of a magnetic field amplitude below a predetermined level or the presence of modulation.

Abstract translation: 近场RF通信器具有电感耦合器（10），以使得能够与RF信号的磁场进行电感耦合。 解调器（102）从电感耦合磁场提取调制。 电力供应商（109）提供独立于任何电感耦合信号的通信器的第一电源，而功率提取器从感应耦合到天线的RF信号导出第二电源。 调节器（206; 1302）基于与参考电压的比较来调节由第一和第二电源中的至少一个提供的电压。 提供了一种调制器（M），用于通过电感耦合来传送具有数据的电感耦合磁场。 在一个示例中，提供调节器控制器以在磁场振幅低于预定水平或存在调制的情况下防止调节器的操作。

公开(公告)号：US07446018B2

公开(公告)日：2008-11-04

申请号：US11466132

申请日：2006-08-22

Applicant: Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

Inventor： Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/2007 ,  H01L21/76251 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/872

Abstract: A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.

Abstract translation: 接合晶片半导体器件包括半导体衬底，设置在半导体衬底的第一主表面上的掩埋氧化物层和多层器件堆叠。 多层器件堆叠包括设置在掩埋氧化物层上的第一导电体的第一器件层，设置在第一器件层上的第二导电体的第二器件层，设置在第二器件上的第一导电体的第三器件层 层和设置在第三器件层上的第二导电体的第四器件层。 在多层器件堆叠中形成沟槽。 台面由沟槽定义。 台面具有第一和第二侧壁。 第一阳极/阴极层设置在多层器件堆叠的第一侧壁上，第二阳极/阴极层设置在多层器件堆叠的第二侧壁上。

公开(公告)号：US07439178B2

公开(公告)日：2008-10-21

申请号：US11675407

申请日：2007-02-15

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/44

CPC classification number: H01L21/78

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract translation: 绝缘体上半导体（SOI）晶片包括具有彼此相对的第一和第二主表面的半导体衬底。 电介质层设置在半导体衬底的第一主表面的至少一部分上。 器件层具有第一主表面和第二主表面。 器件层的第二主表面设置在与半导体衬底相对的电介质层的表面上。 在设备层的第一主表面上限定多个预期的管芯区域。 多个预期的模具区域彼此分离。 多个裸片存取沟槽从第二主表面形成在半导体衬底中。 多个管芯存取沟槽中的每一个通常设置在多个预期管芯区域中的至少一个相应的一个的下方。

公开(公告)号：US20080122040A1

公开(公告)日：2008-05-29

申请号：US11772104

申请日：2007-06-29

Applicant: Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

Inventor： Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varying pitch adapter that converts a first pitch to a second pitch. The adapter comprises a substrate, a plurality of first conductive vias, at least one second conductive via, a first dielectric layer and a second dielectric layer. The substrate has a first main surface and a second main surface. The plurality of first conductive vias extend through the substrate from the first main surface to the second main surface. The second conductive via is disposed in a portion of the first main surface and the second main surface. The second conductive via is coupled to at least one of the plurality of first conductive vias. The first dielectric layer covers at least the portion of the first main surface of the substrate. The second dielectric layer covers at least a portion of the second main surface of the substrate.

Abstract translation: 一种变化的音调适配器，将第一音调转换为第二音高。 适配器包括基板，多个第一导电通孔，至少一个第二导电通孔，第一介电层和第二介电层。 基板具有第一主表面和第二主表面。 多个第一导电通孔从第一主表面延伸穿过基底到第二主表面。 第二导电通孔设置在第一主表面和第二主表面的一部分中。 第二导电通孔耦合到多个第一导电通孔中的至少一个。 第一电介质层至少覆盖基板的第一主表面的部分。 第二电介质层覆盖基板的第二主表面的至少一部分。

公开(公告)号：US20080099924A1

公开(公告)日：2008-05-01

申请号：US11925329

申请日：2007-10-26

Applicant: Cormac MacNamara ,  Hugh Griffin ,  Robin Wilson

Inventor： Cormac MacNamara ,  Hugh Griffin ,  Robin Wilson

IPC: H01L23/48 ,  H01L21/76

CPC classification number: H01L21/76898 ,  B81B2207/096 ,  B81C1/00301 ,  H01L23/481 ,  H01L2224/13099 ,  H01L2924/09701 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench of a predetermined geometric shape is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection.

Abstract translation: 一种制造半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 在第一主表面上的半导体衬底中形成预定几何形状的沟槽。 沟槽延伸到半导体衬底中的第一深度位置。 沟槽衬有介电材料。 沟槽填充有导电材料。 电气部件电连接到在第一主表面露出的导电材料。 盖子安装到第一主表面。 盖子包围电气部件和电气连接。