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公开(公告)号:JPH05219419A
公开(公告)日:1993-08-27
申请号:JP29048591
申请日:1991-10-11
Applicant: SONY CORP
Inventor: KONDO TETSUJIRO , FUJIMORI YASUHIRO , UCHIDA MASASHI , HORISHI MASARU , HASHINO TSUKASA
IPC: H04N5/232
Abstract: PURPOSE:To provide a motion vector detector for a picture capable of detecting the motion vector of the picture with high accuracy. CONSTITUTION:A difference between picture data of each picture element of a block of a current frame and picture data of representative point picture elements of a preceding frame read from a representative point memory 11 is detected by a subtractor circuit 12 and a correlation integration list is generated by a correlation integration list generating circuit 13. A motion vector estimating circuit 14 obtains a coordinate in the middle corresponding to a minimum value of an nth order curved face including the minimum correlation integration value of the coordinate of the minimum correlation integration value of the correlation integration list with respect to a circumferential coordinate to estimate the motion vector.
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公开(公告)号:JPH05137052A
公开(公告)日:1993-06-01
申请号:JP32673491
申请日:1991-11-15
Applicant: SONY CORP
Inventor: KONDO TETSUJIRO , FUJIMORI YASUHIRO , UCHIDA MASASHI , HORISHI MASARU , HASHINO TSUKASA
Abstract: PURPOSE:To quickly decide the camera jiggle of an image by dividing an image covering a single field into plural blocks and checking whether a motion vector is caused by the camera jiggle or not based on the inter-field correlation of the image data on each of plural key point picture element of each block. CONSTITUTION:A key point memory 11 stores the image data on the key point picture element of each of blocks divided from an image covering a single field. The field differential absolute value that is obtained as the subtraction output data on a subtractor circuit 12 is supplied to a correlative integration value production circuit 13. The correlative integration value produced by the circuit 13 is supplied to a motion vector detection circuit 14 and then to a condition deciding circuit 23. The decision output of the circuit 23 is inputted to a frequency distribution production circuit 24. A camera jiggle deciding circuit 25 decides that the motion vector is caused by the camera jiggle if the frequency value of the coordinates corresponding to the motion vector of the image detected by a vector detection part 10 is smaller than a prescribed level in regard of a frequency distribution table produced by the circuit 24.
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公开(公告)号:JPH05110934A
公开(公告)日:1993-04-30
申请号:JP29048391
申请日:1991-10-11
Applicant: SONY CORP
Inventor: KONDO TETSUJIRO , FUJIMORI YASUHIRO , UCHIDA MASASHI , HORISHI MASARU , HASHINO TSUKASA
Abstract: PURPOSE:To provide the motion vector detector for image which is enable to detect the motion vectors of images with high accuracy. CONSTITUTION:The motion vector of the image between one-fields is detected by a first representative point memory FM1, first subtraction circuit SUB1 and a first motion vector detection circuit DET1, and the motion vector of the image between two-fields is detected by a second representative point memory FM2, second subtraction circuit SUB2 and a second motion vector detection circuit DET2. Then, a motion vector synthesizing circuit SYN outputs a motion vector adding and synthesizing the respective motion vectors at a ratio k:k-1 corresponding to a detecting output (k) due to an acceleration detection circuit ACD to detect acceleration for the motion of the image based on the respective motion vectors.
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公开(公告)号:JP2005348093A
公开(公告)日:2005-12-15
申请号:JP2004165453
申请日:2004-06-03
Inventor: TANAKA JUNICHI , SATO KAZUFUMI , HASHINO TSUKASA , YAGASAKI YOICHI
IPC: H04N19/50 , H04N19/105 , H04N19/11 , H04N19/134 , H04N19/139 , H04N19/146 , H04N19/159 , H04N19/176 , H04N19/186 , H04N19/196 , H04N19/46 , H04N19/463 , H04N19/503 , H04N19/51 , H04N19/513 , H04N19/517 , H04N19/52 , H04N19/577 , H04N19/593 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/80 , H04N19/91 , H04N7/32
CPC classification number: H04N19/587 , H04N19/103 , H04N19/132 , H04N19/139 , H04N19/176 , H04N19/61
Abstract: PROBLEM TO BE SOLVED: To provide an image processor with which high image quality encoding is realized, a program and a method thereof. SOLUTION: A motion prediction/compensation circuit 43 does not select a Skip mode and a Direct mode among motion prediction/compensation modes when difference between a predicted motion vector and an actual motion vector exceeds a predetermined reference value. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题:提供实现高图像质量编码的图像处理器,程序及其方法。 解决方案:当预测运动矢量和实际运动矢量之间的差超过预定参考值时,运动预测/补偿电路43不选择运动预测/补偿模式中的跳跃模式和直接模式。 版权所有(C)2006,JPO&NCIPI
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45.
公开(公告)号:JP2004104694A
公开(公告)日:2004-04-02
申请号:JP2002267122
申请日:2002-09-12
Inventor: HASHINO TSUKASA , SUGIYAMA AKIRA
IPC: H04N19/60 , H03M7/30 , H04N19/103 , H04N19/134 , H04N19/172 , H04N19/196 , H04N19/423 , H04N19/85 , H04N7/30
CPC classification number: H04N19/62 , H04N19/115 , H04N19/146 , H04N19/39 , H04N19/63
Abstract: PROBLEM TO BE SOLVED: To realize encoding which provides high picture quality, high compressibility and high editing accuracy and easily utilizes various kinds of image compression technology. SOLUTION: In an arithmetic block 11, a sum signal DVad and a difference signal DVsu of image signals between frames are produced from an input image signal DVin at the interval of two frames. In a bit rate ratio control block 13, control signals CRad and CRsu for controlling a ratio of encoding bit rates of the sum signal and the difference signal in the encoding bit rate are produced based upon the sum signal DVad and the difference signal DVsu. In an encoding processing block 12, an encoded signal DTad of the encoding bit rate based on the control signal CRad is produced from the sum signal DVad by using encoding processing in which the encoding bit rate is varied based upon the control signals CRad and CRsu and further, an encoded signal DTsu of the encoding bit rate based on the control signal CRsu is produced from the difference signal DVsu. COPYRIGHT: (C)2004,JPO
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46.
公开(公告)号:JP2001283531A
公开(公告)日:2001-10-12
申请号:JP2000094751
申请日:2000-03-30
Applicant: SONY CORP
Inventor: KOZAI TOSHINORI , ABE FUMIYOSHI , HAYAKAWA TOMOO , HASHINO TSUKASA
IPC: H04N5/78 , G11B20/12 , G11B20/18 , G11B27/30 , H04N5/782 , H04N5/7826 , H04N5/92 , H04N9/804 , H04N9/806 , H04N9/82 , H04N19/00 , H04N19/65 , H04N19/70 , H04N21/438 , H04N7/24
Abstract: PROBLEM TO BE SOLVED: To record data of an HD video signal on a magnetic tape. SOLUTION: A preamble is formed at the head of each track of the magnetic tape which is formed obliquely along the length and a main sector and a subcode sector are then formed continuously without leaving any gap between them. A postamble is formed right after the subcode sector. In the main sector, data, sound data, search data, AUX data, etc., of the HD video signal are recorded. The main sector is composed of 139 sync blocks of 111-byte length. In each sync block, a Reed-Solomon code as an error correction internal code is composed of 3-byte ID, 96-byte main data, and 10-byte parity C1.
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公开(公告)号:JPH06165165A
公开(公告)日:1994-06-10
申请号:JP33818792
申请日:1992-11-25
Applicant: SONY CORP
Inventor: HASHINO TSUKASA
IPC: H04N19/50 , H03M7/30 , H03M7/36 , H03M7/40 , H04N19/105 , H04N19/139 , H04N19/196 , H04N19/423 , H04N19/46 , H04N19/463 , H04N19/503 , H04N19/51 , H04N19/52 , H04N19/527 , H04N19/533 , H04N19/61 , H04N19/625 , H04N19/65 , H04N19/70 , H04N19/93 , H04N7/137
Abstract: PURPOSE:To obtain a motion vector coding method and its device capable of reducing data value at the time of transmitting or recording an image. CONSTITUTION:A 1st integration value memory 24 is a memory for storing the integration value of the absolute values of differences of data between a block in a range to be searched and a block to be processed which is calculated through a subtractor 21 and an absolute value circuit 26. When the integration of image data for one block in the memory 24 is completed, the contents of the memory 24 are added to that of a 2nd integration value memory 25 and the added value is recorded in the memory 25. Minimum value detecting circuits 28, 29 respectively detect the smallest values in the contents of the memories 24, 25. The output of the circuit 28 is an absolute motion vector, the output of the circuit 29 is the motion vector of the whole picture and the difference between both the outputs becomes a relative motion vector.
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公开(公告)号:JPH06164418A
公开(公告)日:1994-06-10
申请号:JP33526392
申请日:1992-11-20
Applicant: SONY CORP
Inventor: KONDO TETSUJIRO , FUJIMORI YASUHIRO , NAKAYA HIDEO , UCHIDA MASASHI , HASHINO TSUKASA
Abstract: PURPOSE:To provide methods and devices for variable run length encoding and decoding which have a high encoding efficiency with simple procedures and device constitution. CONSTITUTION:A coefficient 0 detecting circuit 140 detects that an input coefficient is O, and a run (0) generating circuit 141 generates a run code corresponding to continuous coefficient 0 in accordance with the control of a control part 146. A coefficient K detecting circuit 142 detects that the inputted coefficient is K, and a run (K) generating circuit 143 generates a run code corresponding to continuous coefficient O. A multiplexing circuit 144 inserts the run code, which is generated in this manner, before the last inputted coefficient and inputs it to a FIFO 145. The control part 146 controls the operation of each part of a run length encoding circuit 14.
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公开(公告)号:JPH0686272A
公开(公告)日:1994-03-25
申请号:JP25353892
申请日:1992-08-31
Applicant: SONY CORP
Inventor: HASHINO TSUKASA , KAWAGUCHI KUNIO
Abstract: PURPOSE:To shorten an arithmetic time by successively comparing the middle calculated results of plural evaluation functions, and moving to the calculation of the new evaluation function between the pre-block and a block to be processed. CONSTITUTION:An input television picture signal is transmitted to a high speed vector detecting circuit 10 and a one frame memory 11. The circuit 10 successively compares an in-block residual absolute value sum as the evaluation function calculated between a reference block at a corresponding spatial position and a block T with the cumulative middle result of the in-block residual absolute value at the time of searching the in-block residual absolute value sum being the evaluation function calculated between the block T and the arbitrary pre- block in a prescribed inspection space I, by referring to a moving vector held in a delay 12 for a reference vector. Then, when the cumulative middle result is more than the in-block residual absolute value sum, the calculation of the in-block residual absolute value sum is stopped, and the calculation of the new in-block residual absolute value sum between the next pre-block in the prescribed inspection space I and the block T is started.
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公开(公告)号:JPH05153464A
公开(公告)日:1993-06-18
申请号:JP33802491
申请日:1991-11-28
Applicant: SONY CORP
Inventor: KONDO TETSUJIRO , FUJIMORI YASUHIRO , UCHIDA MASASHI , HORISHI MASARU , HASHINO TSUKASA
IPC: H04N5/232
Abstract: PURPOSE:To surely discriminate whether or not a detected motion vector results from a jiggle. CONSTITUTION:A motion vector detection section 13 detects a motion vector based on a field difference absolute value detected by a field difference detection section 11, a stationary camera scene discrimination section 12 discriminates a stationary camera scene, and a minimum value detection section 14 detects it that an integration of coordinates corresponding to representative point picture elements is a minimum value in relation to a correlation integration table for each macro block. Then a jiggle discrimination section 15 discriminates whether or not the motion vector results from a jiggle based on the discrimination output of the stationary camera scene discrimination section 12 and the detection output of the minimum value detection section 14.
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