公开(公告)号：JP2007310767A

公开(公告)日：2007-11-29

申请号：JP2006141103

申请日：2006-05-22

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MASUDA TAKASHI

IPC: G06F9/445

Abstract: PROBLEM TO BE SOLVED: To further efficiently perform processing for updating software. SOLUTION: A CE apparatus 11 stores timing information for expressing the timing for making access in the next place to a service server 12 for providing updating software, and acquires an updating list file from the service server 12, by making access to the service server 12, when becoming its timing. The CE apparatus 11 determines whether or not to acquire the updating software by whether or not software of a newer version than a version of the software held by the CE apparatus 11 is stored in the service server 12 from the updating list file. This invention can be applied to, for example, an information processor for executing processing by using the software. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：进一步有效地执行更新软件的处理。 解决方案：CE设备11将用于表示下一次访问的定时的定时信息存储到用于提供更新软件的服务服务器12，并且从服务服务器12获取更新列表文件，通过访问 服务服务器12成为其定时。 CE装置11通过是否将更新版本的软件比由CE装置11所持有的软件的版本更新而从更新列表文件存储在服务服务器12中来确定是否获取更新软件。 本发明可以应用于例如用于通过使用软件执行处理的信息处理器。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH01176170A

公开(公告)日：1989-07-12

申请号：JP33530187

申请日：1987-12-29

Applicant: SONY CORP

Inventor： MASUDA TAKASHI ,  OKAZAKI SAKAE ,  YAMAZAKI HIROSHI

IPC: H04N5/278

Abstract: PURPOSE:To output a title picture on the entire pattern by writing an input video signal into a memory means as a digitized picture data, synthesizing the picture data read from the memory means with a picture signal at the outside of the title picture depending on the capacity of the memory means and forming the title picture signal. CONSTITUTION:In case of registering a title picture, a picture data being a digitized input video signal is written in a memory means 13. A title circuit 12 in the event of inserting the title picture, forms a picture signal at the outside of the title picture depending on the capacity of the memory means 13, synthesizes the picture signal with the picture data read from the memory means 13 to form and output the title picture signal forming one title picture. Thus, it is possible to output the title picture on the entire screen.

公开(公告)号：JPS61103378A

公开(公告)日：1986-05-21

申请号：JP22540284

申请日：1984-10-26

Applicant: Sony Corp

Inventor： MASUDA TAKASHI ,  KOBAYASHI YOICHI ,  IO HIDEAKI

IPC: G11B31/00 ,  G11B5/027 ,  G11B15/467 ,  G11B27/02 ,  H04N5/782 ,  H04N5/7826

Abstract: PURPOSE: To simplify the mechanism and operation of a tape drive system and to improve the accuracy of joints by synchronizing a recording signal system with a control pulse reproduced from a tape in case of joint image pickup.
CONSTITUTION: In case of the video recording mode, a generating circuit 40 generates a vertical synchronizing signal Sv and a horizontal synchronizing signal Sh, they are fed to an image pickup tube 21 and a control pulse CTL having a frequency is generated and fed to a head 16 through a recording side contact R of a switch circuit 36 and recording at the edge of a tape 1. In bringing the mode to the video recording pause mode by turning on a switch 51, the head 16 reproduces the control pulse CTL, which is fed to a control circuit 50 via the switch 36 and a reproducing amplifier 37. Then the control circuit 50 checks the period of the CTL and confirms that the tape running is stabilized, then a reset pulse synchronously with the CTL is given to the generating circuit 40.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：简化磁带驱动系统的机制和操作，并通过将记录信号系统与从磁带再现的控制脉冲同步来提高关节的精度，以防联合图像拾取。 构成：在视频记录模式的情况下，发生电路40产生垂直同步信号Sv和水平同步信号Sh，将它们馈送到图像拾取管21，产生具有频率的控制脉冲CTL并将其馈送到 头16通过开关电路36的记录侧触点R并在磁带1的边缘进行记录。通过开启开关51使模式进入视频记录暂停模式，磁头16再现控制脉冲CTL，其中 经由开关36和再现放大器37馈送到控制电路50.然后，控制电路50检查CTL的周期并确认磁带运行稳定，然后将与CTL同步的复位脉冲发送给生成 电路40。

公开(公告)号：JP2014183531A

公开(公告)日：2014-09-29

申请号：JP2013058320

申请日：2013-03-21

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ZHOU ZHIWEI ,  MASUDA TAKASHI ,  FUJIWARA TETSUYA

IPC: H03L7/093

CPC classification number: H03L7/087 ,  H03L7/095 ,  H03L7/0995

Abstract: PROBLEM TO BE SOLVED: To provide a phase synchronization circuit for reducing a stationary phase error and a clock data recovery circuit.SOLUTION: The output signal line of a charge pump is separated in accordance with charge currents and discharge currents to reduce a stationary phase error which becomes a problem in the case of accelerating a clock data recovery circuit. Furthermore, a loop filter is configured so as to independently act with respect to the charge currents and the discharge currents. Furthermore, a voltage control oscillator is also configured such that an oscillation frequency is controlled by receiving a first voltage signal based on the charge currents and a second voltage signal based on the discharge currents.

Abstract translation: 要解决的问题：提供一种减少稳定相位误差的相位同步电路和时钟数据恢复电路。解决方案：电荷泵的输出信号线根据充电电流和放电电流分开，以减少静态相位误差 这在加速时钟数据恢复电路的情况下成为问题。 此外，环路滤波器被配置为相对于充电电流和放电电流独立地起作用。 此外，电压控制振荡器还被配置为使得通过基于充电电流接收第一电压信号和基于放电电流的第二电压信号来控制振荡频率。

公开(公告)号：JP2005328385A

公开(公告)日：2005-11-24

申请号：JP2004145341

申请日：2004-05-14

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MASUDA TAKASHI ,  ABE MASAMI

IPC: H04J11/00 ,  H04B1/16

Abstract: PROBLEM TO BE SOLVED: To simplify a filter and its control circuit, reduce an area for an integrated circuit, and also reduce power consumption of a multichannel radio receiving device because its channel filter circuit is complicated and a great amount of power is consumed.
SOLUTION: The radio receiving device comprises an oscillator 20 for generating an oscillating signal on the basis of a reference signal from a reference oscillator 40, a frequency converter 14a which is provided with an input signal and an oscillating signal from the oscillator and converts frequencies, a filter 15a which is connected to the frequency converter and varies the state variable of the filter by a first control signal, an arithmetic circuit 50 for arithmetic processing of an filter output signal, a frequency divider 42 which is connected to the reference oscillator and divides the reference signal by a second control signal from the arithmetic circuit, and a control circuit 21 which is connected to the frequency divider and varies the state variable of the filter.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了简化滤波器及其控制电路，减少集成电路的面积，并且还降低多通道无线电接收装置的功耗，因为其信道滤波器电路复杂并且大量的功率是 消耗。 解决方案：无线电接收装置包括：振荡器20，用于根据来自参考振荡器40的参考信号产生振荡信号;频率转换器14a，其设置有来自振荡器的输入信号和振荡信号， 转换频率，连接到变频器并通过第一控制信号改变滤波器的状态变量的滤波器15a，用于滤波器输出信号的算术处理的运算电路50，连接到参考的分频器42 振荡器并通过来自运算电路的第二控制信号对参考信号进行分频，以及连接到分频器并改变滤波器的状态变量的控制电路21。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH11239284A

公开(公告)日：1999-08-31

申请号：JP4074498

申请日：1998-02-23

Applicant: SONY CORP

Inventor： YOSHIDA CHISATO ,  MASUDA TAKASHI

IPC: H04N5/225 ,  H04N5/232 ,  H04N5/335 ,  H04N5/345 ,  H04N5/357 ,  H04N5/376 ,  H04N101/00

Abstract: PROBLEM TO BE SOLVED: To display images with excellent image quality and to quickly record the photographing images of a desired resolution by simple constitution. SOLUTION: In the case of obtaining a still image of an object image by the desired resolution in which a picture element number is less than the effective picture element number of an image pickup element 15, a zoom driving circuit 13 is controlled by a CPU 60 so as to reduce and image-form the object image in the area of the image pickup element 15 corresponding to the desired resolution. The signals of the area where the object image is reduced and image- formed are selected in a memory control part 51 from image data signals Dyc obtained by processing the signals from the element 15 and the signals of the still image of the desired resolution are recorded in a memory part 38. In the setting of a photographing area, the object image is reduced corresponding to the display picture element number of a display part 30 and image-formed on the element 15. The signals of the area where the object image is image- formed are selected in the memory control part 51, video signals SVBout are generated in a video interface part 53 by using the selected signals Dycd and finder images are displayed at the display part 30.

公开(公告)号：JPH031411A

公开(公告)日：1991-01-08

申请号：JP13635789

申请日：1989-05-30

Applicant: SONY CORP

Inventor： IDE YOSHIHIRO ,  MASUDA TAKASHI

IPC: H04N5/225 ,  H01H13/02

Abstract: PURPOSE:To make it possible to use an operational part of an operational lever as a finger rest during image recording by forming the operational lever to be almost circular, projection-forming the operational part in a part of outer side of the lever, and attaching a recording button in the circular inside of the operational level. CONSTITUTION:A recording button 40 is locked or unlocked freely by an operational level 42 which is so supported in the way being able to rotate freely in a caved cylindrical 41 formed unitedly in a back plane 3 of a grip part 3. The operational lever 42 is made of resin and has almost circular cylindrical shape, and an operational part 42b is projected and unitedly formed in a part of outer side of a circular part 42a, and an cylindrical axis part 42c into which an axis part 40b of the recording button 40 is inserted is unitedly formed in the down side of bottom plane of the trunk 42a. Consequently, the operational part of the operational lever can be used as a finger rest during image recording.

公开(公告)号：JPS61148557A

公开(公告)日：1986-07-07

申请号：JP27254784

申请日：1984-12-24

Applicant: SONY CORP

Inventor： SATO MITSURU ,  OTSU YOSUKE ,  MASUDA TAKASHI

IPC: H04L29/08 ,  G06F13/00 ,  G06F13/42

Abstract: PURPOSE:To transfer data surely by sending a start signal from the first microcomputer to the second microcomputer and sending back clocks from the second microcomputer to the first microcomputer and transferring data from the first microcomputer to the second microcomputer. CONSTITUTION:In case of data transfer from the first microcomputer A to the second microcomputer B, a start bit which falls from the high level to the low level at a timing t1 is sent from the microcomputer A to the microcom puter B to report the start of data transfer. Then, the microcomputer B detects the start of transfer and sends a clock to the microcomputer A at a timing t2. When receiving the clock after sending the start bit, the microcomputer A judges that the microcomputer B detects the start of transfer, and the micro computer A sends the first data, for example, the high level immediately. After reading this data H at a timing t3, the microcomputer sends the next clock to the microcomputer A at a timing t4. hereafter, data are sent and read and clocks are sent repeatedly at timings t5, t6- similarly.

公开(公告)号：JPS58186825A

公开(公告)日：1983-10-31

申请号：JP6942482

申请日：1982-04-23

Applicant: Sony Corp

Inventor： MIKAMI TSUTOMU ,  MASUDA TAKASHI ,  KAI KIYOSHI

IPC: H03K17/22 ,  G06F1/24 ,  G06F1/26

CPC classification number: G06F1/24

Abstract: PURPOSE:To select a logical output in a resetting period optionally by connecting an additional circuit which has high output impedance during the resetting period to the output side of the output port register of a logical output impedance IC. CONSTITUTION:When a reset pulse RS is supplied to a terminal 6 after power-on operation, a data signal DT is supplied from a computer 1 to the input register 3 of a latch IC2 for extension, but it is not transferred to the output register 4. The Q output of an FF circuit 9 is on a level L, so the respective NAND circuits 10 and NAD circuits 11 of logical circuits 8 (i=0-n-1) of the additional circuit 7 are closed and the outputs of the circuits 10 and 11 are on the levels H and L respectively. Therefore, MOSFETs 12 and 13 are both off and high output impedance is obtained at each terminal T3; and terminals connected to a power source B through a resistance 11 or grounded are on the levels H and L respectively and terminals in a floating state sill have the high impedance. Output terminals 10n and 10n+1 are set on the level H or L optionally.

Abstract translation: 目的：为了在复位周期内选择逻辑输出，可选择在复位期间将具有高输出阻抗的附加电路连接到逻辑输出阻抗IC的输出端口寄存器的输出端。 构成：在通电操作之后，当将复位脉冲RS提供给端子6时，数据信号DT从计算机1提供给用于扩展的锁存器IC2的输入寄存器3，但不被传送到输出寄存器 FF电路9的Q输出处于电平L，因此附加电路7的逻辑电路8（i = 0-n-1）的各个NAND电路10和NAD电路11（i = 0-n-1）关闭，并且输出 电路10和11分别在电平H和L上。 因此，MOSFET 12和13均断开，并且在每个端子T3处获得高的输出阻抗; 并且通过电阻11或接地连接到电源B的端子分别在电平H和L上，并且浮置状态的端子中的端子具有高阻抗。 输出端子10n和10n + 1可选地设置在电平H或L上。

公开(公告)号：JPS5461825A

公开(公告)日：1979-05-18

申请号：JP12839877

申请日：1977-10-26

Applicant: SONY CORP

Inventor： YAMAGIWA KAZUO ,  NIIMURA TSUTOMU ,  MASUDA TAKASHI

IPC: G11B20/02 ,  G11B5/027 ,  H04N9/70 ,  H04N9/793

Abstract: PURPOSE:To obtain tolerance of the number of pins by controlling the cutting off of signals, by mixing and applying a color signal and DC control signal to either differential amplifier. CONSTITUTION:To the base of transistor Tr3 of either one of differential amplifiers 3 and 4, a mixed signal of a color signal and DC control signal is supplied, and a constant potential voltage is to the input of the other Tr4; and this DC control signal when containing a color signal has a fixed voltage and when no color signal has a voltage below a fixed voltage, and constant-potential signals are extracted from differential amplifiers 35 and 36 regardless of the existence of the color signal. Then, a signal relating to signals of differential amplifiers 3 and 4 is supplied to the base of the Tr35 of either differential amplifier 3 or 4, and a constant potential is to the base of the other Tr36, so that amplifiers 35 and 36 will output signals with a constant potential constantly.