公开(公告)号：JP2003338057A

公开(公告)日：2003-11-28

申请号：JP2003180562

申请日：2003-06-25

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TSUTSUI KEIICHI ,  IGARASHI KATSUJI

IPC: G11B7/085 ,  G11B7/09

Abstract: PROBLEM TO BE SOLVED: To exactly focus on each of the recording layers of an optical disk having a plurality of the recording layers.
SOLUTION: After starting the optical disk at a step S1, a focus offset position optimal to the prescribed recording layer of the optical disk is searched at a step S2. This search is performed by varying an offset value stepwise to retrieve the offset value maximizing the amplitude of a tracking error signal. When the optimal focus offset position is searched, the value is stored at a step S3. Similar processing is performed at the other recording layers. When a command of reproduction to a prescribed recording layer is inputted at a step S8, focus jump to the recording layer is performed at a step S9. Then, an optimal focus offset value searched and stored in advance is read and added to a focus error signal at a step S10. This method can be applied to an optical disk drive.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：精确地对准具有多个记录层的光盘的每个记录层。 解决方案：在步骤S1中启动光盘之后，在步骤S2中搜索对光盘的规定记录层最佳的聚焦偏移位置。 通过逐步改变偏移值来获取最大化跟踪误差信号的幅度的偏移值来执行该搜索。 当搜索最佳对焦偏移位置时，在步骤S3存储该值。 在其他记录层进行类似的处理。 当在步骤S8输入对规定记录层的再现命令时，在步骤S9执行到记录层的聚焦跳转。 然后，在步骤S10中，预先搜索和存储的最佳聚焦偏移值被读取并添加到聚焦误差信号。 该方法可以应用于光盘驱动器。 版权所有（C）2004，JPO

公开(公告)号：JP2003233915A

公开(公告)日：2003-08-22

申请号：JP2002029825

申请日：2002-02-06

Applicant: SONY CORP

Inventor： FUKUMOTO ATSUSHI ,  TSUTSUI KEIICHI

IPC: G11B7/24 ,  G11B7/09

Abstract: PROBLEM TO BE SOLVED: To perform satisfactory recording or reproducing operation by easily and speedly optimizing a focus error detecting state. SOLUTION: By a control part 180, a focus offset signal H is changed and added in an adjustment area, and simultaneously the output of a jitter detecting part 130 is monitored to detect the focus offset amount of a best jitter. Then, the offsets generated in focus error signals F in respective land and groove obtained in the adjustment area are stored in a memory. At the recording/ reproducing operation, when moved to the land or groove area, such an operation is carried out that the offset amounts optimum for each previously stored in the memory are added to the focus error signals F as a signal H. Thus, the recording/reproducing operation is performed in the state the optimum focus state is maintained for each. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH09312024A

公开(公告)日：1997-12-02

申请号：JP12669496

申请日：1996-05-22

Applicant: SONY CORP

Inventor： KOMAZAKI TAKAHIRO ,  TSUTSUI KEIICHI

IPC: G11B21/08 ,  G11B7/00 ,  G11B7/004 ,  G11B7/085 ,  G11B7/09

Abstract: PROBLEM TO BE SOLVED: To obtain the signal (Miller signal) to which a traverse signal is accurately binarized promptly after the reproduction of the scratched part on an optical disk when such a part is reproduced. SOLUTION: In a traverse signal discriminating part 4, the traverse signal which is a low frequency part of the reproduced signal, is separated from the reproduced signal and supplied to a hold circuit 5B. The traverse signal is subjected to bottom hold in the hold circuit 5B and a bottom hold signal is outputted. On the other hand, a defect detecting circuit 11 detects whether or not the defect exists in the reproduced signal, and when the defect is detected, a defect signal of H-level is supplied to a hold voltage reset circuit 12. During the H-level defect signal is received by the hold voltage reset circuit 12, a capacitor incorporated in the hold circuit 5B is discharged, thereby the holding operation is stopped.

公开(公告)号：JP2014086062A

公开(公告)日：2014-05-12

申请号：JP2012237383

申请日：2012-10-29

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKANISHI KENICHI ,  FUJINAMI YASUSHI ,  TSUTSUI KEIICHI

IPC: G06F12/16

CPC classification number: G06F11/1048 ,  G11C13/0002 ,  G11C13/004 ,  G11C2029/0411

Abstract: PROBLEM TO BE SOLVED: To provide a storage control device capable of controlling a read request according to a state of error correction in a memory available for both of read of standard precision and read of high precision.SOLUTION: A standard read request section requests a standard precision read to a read address on a memory. Responding to the read request of standard precision, the error correction part performs an error correction based on data returned from the memory and an error correction code. When an error which cannot be corrected by the error correction, a high precision read request section makes a request again to read the read address at a precision higher than the standard precision.

Abstract translation: 要解决的问题：提供一种能够根据可用于标准精度读取和高精度读取的存储器中的错误校正状态来控制读取请求的存储控制装置。解决方案：标准读取请求部分请求 标准精度读取到存储器上的读取地址。 响应于标准精度的读取请求，纠错部分基于从存储器返回的数据和纠错码执行纠错。 当错误校正无法纠正的错误时，高精度读取请求部分再次请求以比标准精度更高的精度读取读取地址。

公开(公告)号：JP2013228767A

公开(公告)日：2013-11-07

申请号：JP2012098316

申请日：2012-04-24

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKANISHI KENICHI ,  TSUTSUI KEIICHI ,  FUJINAMI YASUSHI ,  ADACHI NAOHIRO ,  OKUBO HIDEAKI ,  SHINBASHI TATSUO ,  ISHII TAKESHI

IPC: G06F12/16

CPC classification number: G06F9/3004 ,  G11C16/3418 ,  G11C29/08 ,  G11C29/52 ,  G11C2029/0401

Abstract: PROBLEM TO BE SOLVED: To suppress an increase in the number of defective cells in a nonvolatile memory.SOLUTION: A second rewrite processing unit executes first rewrite processing in which a memory cell where one of two values is written is rewritten with the other value. A second rewrite processing unit executes second rewrite processing in which a memory cell where the other of the two values is written is rewritten with the one value. If an error occurs during the first rewrite processing, a first retry control unit causes the second rewrite processing to be executed in the memory cell where the first rewrite processing has been executed, and then causes the first rewrite processing to be executed again.

Abstract translation: 要解决的问题：抑制非易失性存储器中缺陷单元数量的增加。解决方案：第二重写处理单元执行其中写入两个值之一的存储单元被另一个值重写的第一重写处理。 第二重写处理单元执行第二重写处理，其中写入两个值中的另一个的存储单元用该值重写。 如果在第一重写处理期间发生错误，则第一重试控制单元使得在执行了第一重写处理的存储单元中执行第二重写处理，然后再次执行第一重写处理。

公开(公告)号：JP2013092854A

公开(公告)日：2013-05-16

申请号：JP2011233602

申请日：2011-10-25

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKANISHI KENICHI ,  TSUTSUI KEIICHI

IPC: G06F12/16 ,  G06F3/06

CPC classification number: G06F11/1048

Abstract: PROBLEM TO BE SOLVED: To perform error detection and correction processing by the use of error correcting codes suited to an access size without straining the storage capacity of a nonvolatile memory.SOLUTION: A first error detection unit is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. A second error detection unit is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold unit different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold unit.

Abstract translation: 要解决的问题：通过使用适合于访问大小的纠错码来执行错误检测和校正处理，而不会使非易失性存储器的存储容量变紧。 解决方案：第一错误检测单元被配置为根据从存储器读取的第一数据单元和对应于第一数据单元的第一错误检测代码执行错误检测。 第二错误检测单元被配置为如果对应于小于第一数据单元的第二数据单元的第二错误检测代码被保存在与存储器不同的错误检测代码保持单元中，则根据第二数据执行错误检测 从存储器读取的单元和保存在错误检测代码保持单元中的第二错误检测代码。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011039585A

公开(公告)日：2011-02-24

申请号：JP2009183517

申请日：2009-08-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKANISHI KENICHI ,  TSUTSUI KEIICHI ,  KOSHIYAMA JUNICHI

IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02 ,  G11C16/02 ,  G11C16/06

CPC classification number: H03M13/6505 ,  G06F11/1068 ,  H03M13/00 ,  H03M13/6508

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile random access memory and a nonvolatile memory system which, while being randomly accessible, can retain data even after power is turned off and which make it possible to add an ECC (Error Correcting Code) matching an application. SOLUTION: A NVRAM (nonvolatile random access memory) 21 includes: a nonvolatile storage area 211 that is randomly accessible and includes two areas, i.e., a data area and an ECC (error-correcting-code) area to store an error correcting (ECC) code; and a nonvolatile storage area control unit 212 that provides a nonvolatile storage area setting function for setting a data size used when the data area is accessed, as the data area unit size. The nonvolatile storage area control unit 212 includes functions to manage the data area and the ECC area based on the set data area unit size and to assign the ECC area with the ECC area unit size set by the nonvolatile storage area control unit to each data area unit size. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非易失性随机存取存储器和非易失性存储器系统，其在随机访问的同时即使在电源关闭之后也可以保留数据，并且使得可以添加ECC（纠错码） 匹配应用程序。 解决方案：NVRAM（非易失性随机存取存储器）21包括：非易失性存储区域211，其是可随机访问的，并且包括两个区域，即数据区域和用于存储错误的ECC（纠错码）区域 校正（ECC）代码; 以及非易失性存储区域控制单元212，其提供用于设置访问数据区域时使用的数据大小的非易失性存储区域设置功能作为数据区域单元大小。 非易失性存储区域控制单元212包括基于设置的数据区域单元大小来管理数据区域和ECC区域的功能，并且将由非易失性存储区域控制单元设置的ECC区域单元大小的ECC区域分配给每个数据区域 单位尺寸 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009059253A

公开(公告)日：2009-03-19

申请号：JP2007227207

申请日：2007-08-31

Applicant: Sony Corp ,  ソニー株式会社

Inventor： AOKI SADATAKA ,  TSUTSUI KEIICHI

IPC: G06K19/077

CPC classification number: G06K19/077 ,  G06K13/085 ,  G06K19/07 ,  G06K19/07345 ,  G06K19/07732 ,  G06K19/07741 ,  G06K19/07743

Abstract: PROBLEM TO BE SOLVED: To provide a card type peripheral device with its size reduction achieved, having a switch for disabling recording/erasure to a card, and allowing efficient handling of the card in host equipment by conveying information thereabout to the outside by a card terminal. SOLUTION: This card type peripheral device has: an electronic component including a memory stored inside a case body; a terminal part 102 formed with connection terminals connectable with the connection target equipment; and the switch 110 for forbidding the recording to the memory. The card type peripheral device includes a signal terminal 1022 capable of transmitting a state of the switch 110 to the connection target equipment side. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供实现其尺寸减小的卡式外围设备，具有用于禁止对卡进行记录/擦除的开关，并且通过将信息传送到外部来允许主机设备中的卡的有效处理 由卡终端。 解决方案：该卡型外围设备具有：电子部件，其包括存储在壳体内的存储器; 形成有可与连接目标设备连接的连接端子的端子部分102; 以及用于禁止记录到存储器的开关110。 卡式外围设备包括能够将连接目标设备侧的开关110的状态发送的信号终端1022。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006195569A

公开(公告)日：2006-07-27

申请号：JP2005004299

申请日：2005-01-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： SATORI KENICHI ,  TSUTSUI KEIICHI ,  NAKANISHI KENICHI ,  BANDO HIDEAKI ,  OKUBO HIDEAKI ,  AOKI SADATAKA ,  KONNO TAMAKI

IPC: G06K19/07 ,  G06F3/06 ,  G06F3/08 ,  G06F12/00 ,  G06F12/06

CPC classification number: G06F3/0656 ,  G06F3/0613 ,  G06F3/0679 ,  G11C7/22

Abstract: PROBLEM TO BE SOLVED: To properly vary speeds of data write processing and data read processing. SOLUTION: On receipt of a grade designation signal for designating a grade from a set unit 11, a controller 3 of a semiconductor memory unit 1 executes logic block assignment processing so that the data write processing and the data read processing can be executed in parallel to a flash memory chip CP of which the number corresponds to a grade designated by the received grade designation signal. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：适当地改变数据写入处理和数据读取处理的速度。 解决方案：半导体存储器单元1的控制器3在从设定单元11接收到用于指定等级的等级指定信号时，执行逻辑块分配处理，从而可以执行数据写入处理和数据读取处理 与闪存芯片CP并联，其中数字对应于由接收的等级指定信号指定的等级。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006119961A

公开(公告)日：2006-05-11

申请号：JP2004307976

申请日：2004-10-22

Applicant: Renesas Technology Corp ,  Sony Corp ,  ソニー株式会社 ,  株式会社ルネサステクノロジ

Inventor： AOKI SADATAKA ,  BANDO HIDEAKI ,  TSUTSUI KEIICHI ,  NISHIZAWA HIROTAKA ,  OSAWA KENJI ,  TOTSUKA TAKASHI

IPC: G06K19/07

CPC classification number: G06K19/07732 ,  G06K19/07735 ,  G06K19/07743 ,  G06K19/07769

Abstract: PROBLEM TO BE SOLVED: To stably perform data communication without being affected by noise, in a memory card to which a module for data communication is newly added. SOLUTION: The memory card 100 includes a holding body 20 like a thin plate, a memory 24 buried in the holding body 20, a plurality of first contacts 2 to 10 connected to the memory 24, a data communication part 26 buried in the holding body 20, and two second contacts 11 and 12 connected to the data communication part 26. The two second contacts 11 and 12 are arranged at the end of a column R1 where only the plurality of first contacts 2 to 10 are arrayed. One first contact 10 placed at the end of the column R1 is a ground terminal. That is, the first contact 10 adjacent to the second contact 11 out of the plurality of first contacts 2 to 10 is the ground terminal. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了稳定地执行不受噪声影响的数据通信，在新添加了用于数据通信的模块的存储卡中。 存储卡100包括：薄板状的保持体20，埋藏在保持体20中的存储器24，与存储器24连接的多个第一触点2〜10，埋入 保持体20和连接到数据通信部分26的两个第二触点11和12.两个第二触点11和12布置在仅排列多个第一触点2至10的列R1的端部。 放置在列R1的端部的一个第一触头10是接地端子。 也就是说，与多个第一触点2至10中的第二触点11相邻的第一触点10是接地端子。 版权所有（C）2006，JPO＆NCIPI