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公开(公告)号：JPH04291952A
公开(公告)日：1992-10-16
申请号：JP8141091
申请日：1991-03-20
Applicant: SONY CORP
Inventor： OGAWA TETSUO
IPC: H01L21/8232 , H01L21/8248 , H01L27/06
Abstract: PURPOSE:To achieve that a bipolar transistor and a JFET whose breakdown strength is high and whose mutual conductance is high are integrated into one chip and to reduce the cost of the title device. CONSTITUTION:A formation region 4 for a bipolar transistor and a formation region 5 for a JFET are isolated by a transistor isolation region 13. A collector diffusion layer 15 is formed in the upper layer of a semiconductor substrate 12 in the formation region 14 for the former. A base diffusion layer 16 and a collector extraction diffusion region 19 are formed in an epitaxial layer 11 formed on the surface of the semiconductor substrate 12 by sandwiching an element isolation region 18 in a state that they are connected to the collector diffusion layer. An emitter diffusion layer 17 is formed in a part of the upper layer of the base diffusion layer 16. A bottom gate diffusion layer 20 is formed in the upper layer of the semiconductor substrate 12 in the formation region 5 for the latter. A channel formation region 21 is formed in the epitaxial layer 11 in a state that it is connected to the bottom gate diffusion layer. A top gate diffusion layer 22 is formed on its surface. Source-drain diffusion layers 23, 24 are formed on both sides of them.
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公开(公告)号：JPS62197983A
公开(公告)日：1987-09-01
申请号：JP3839986
申请日：1986-02-25
Applicant: SONY CORP
Inventor： OGAWA TETSUO
IPC: G11B27/36
Abstract: PURPOSE:To stably and exactly perform the monitoring operation of preview mode, by setting a delay recording signal in which a delayed quantity equivalent to the difference of angle of rotation between a recording head and a reproducing head is supplied to a recording signal, as a monitoring output. CONSTITUTION:As a delay circuit 14, a circuit having a delayed quantity (tau) corresponding to the difference theta of the angle of rotation between a magnetic head 6 and a reproducing head 8, is used, and it is constituted so that a delay digital recording signal is formed by giving the delayed quantity (tau) to the digital recording signal supplied from a recording processing circuit 2, and it is supplied to a reproduction processing circuit 12 through a switch circuit 10. As for the delay digital recording signal, the phase of which is coincided with that of a digital reproducing signal reproduced from a magnetic tape 7 by the reproducing head 8, and by controlling the switch circuit 10 so as to select the delay digital recording signal in the preview mode, a phase continuity between a signal recorded newly and the reproducing signal following the signal can be secured.
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公开(公告)号：JPS61276490A
公开(公告)日：1986-12-06
申请号：JP11776485
申请日：1985-05-31
Applicant: SONY CORP
Inventor： SUMA TETSURO , OGAWA TETSUO
Abstract: PURPOSE:To prevent the occurrence of outrunning of address by detecting the reading/writing address difference of buffer memory of a reproducing circuit of VTR and controlling the jumping of reading address at the time of reproducing at speed of (1+ or -alpha) times. CONSTITUTION:Difference Adj of addresses from the read address write address generating circuits 15, 13 of a buffer memory 14 of plural, (n) etc. fields is detected by a comparator circuit 18. At the time of (1+alpha) times reproducing, when read address is [(n-1)+alpha
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公开(公告)号：JPS61267416A
公开(公告)日：1986-11-27
申请号：JP10888085
申请日：1985-05-21
Applicant: SONY CORP
Inventor： SUMA TETSURO , TATEZAWA KAICHI , OGAWA TETSUO , KOMINAMI HISANORI , ABE TAKAO , KOTANI HIROKI
Abstract: PURPOSE:To eliminate the need for a memory for rearrangement only by arranging a memory rearranging a series of an inner code into a series of an external code between a decoder of the inner coder and a decoder of the external code. CONSTITUTION:A reproduction input section 11 is provided with a PLL circuit for clock recovery synchronously with a recovered data, a serial/parallel converting circuit, a block synchronous detection circuit and an address recovery circuit or the like. The time series of the recovered data corresponds to the time series of the inner code and fed to a decoder 12 of the inner code to decode the inner code. A reproduced video data and an N/O flag outputted from a buffer memory 13 are fed to a decoder 14 for the external code and the decoder 14 for the external code applies decoding of (m+2, m) reed Solomon code. The output data of the decoder 14 of the external code is fed to an error correction circuit 15 to interpolate an error data. The output data of the error correction circuit 15 is extracted at an output terminal 17 via a D/A converter 16.
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公开(公告)号：JP2004268307A
公开(公告)日：2004-09-30
申请号：JP2003059245
申请日：2003-03-05
Inventor： TOMITA MANABU , KUWABARA SOICHI , HIRASHIMA SHIGEYOSHI , NAKAMURA MASATO , OGAWA TETSUO , EGUCHI TAKEO
Abstract: PROBLEM TO BE SOLVED: To prevent degradation of image quality due to uneven density or a white streak. SOLUTION: A pair of heating resistors 102a and 102b arranged side by side in the substantially same direction as the traveling direction of a recording sheet are fed with power of different magnitude or fed with power while shifting the timing. Ejecting direction of an ink liquid drop i is substantially aligned with the traveling direction of a recording sheet by varying power supply periodically. Since ejecting direction can be varied periodically, ink drops adjacent in the traveling direction of the recording sheet at the shooting point of the ink drop i on the recording sheet compensate the boundaries each other thus preventing a white streak in the direction substantially perpendicular to the traveling direction of the recording sheet or uneven density of color. COPYRIGHT: (C)2004,JPO&NCIPI
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Patent Agency Ranking
公开(公告)号：JPH10117327A
公开(公告)日：1998-05-06
申请号：JP25237397
申请日：1997-09-17
Applicant: SONY CORP , SONY ELECTRONICS INC
Inventor： OGAWA TETSUO , KIRIYAMA HIROSHI , KATO TOMOKIYO , KIKUCHI HIROAKI , FREEMAN LUKE
IPC: H04N5/93 , G11B15/02 , G11B27/022 , G11B27/032 , H04N5/783
Abstract: PROBLEM TO BE SOLVED: To provide a reproduction time variable method for a video signal where a reproduction time if changed consciously, while preventing deterioration in type quality of the video signal. SOLUTION: A synchronization signal generator 26 generates plural synchronization signals, having a different field frequency from a prescribed absolute reference synchronization signal corresponding to a reproduction speed control signal. A modified player 17 receives any of the plural synchronization signals as an external reference signal to change a reproduction speed of a video signal recorded on a cassette 13. A scanning line converter 18 converts a scanning line number of the video signal reproduced from the player 17. A field frequency converter 19 converts the field frequency of the reproduction video signal from the converter 18, so as to have the same frequency as the prescribed absolute reference synchronization signal.
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公开(公告)号：JPH1098645A
公开(公告)日：1998-04-14
申请号：JP20667497
申请日：1997-07-31
Applicant: SONY CORP , SONY ELECTRONICS INC
Inventor： OGAWA TETSUO , KIRIYAMA HIROSHI , KATO TOMOKIYO , KIKUCHI HIROAKI , ROOKE FREEMAN
IPC: H04N5/253
Abstract: PROBLEM TO BE SOLVED: To provide an image information conversion method capable of improving operating efficiency by using a telecine device only once and reducing frequency of opportunity of giving damage to a movie film. SOLUTION: A telecine device 11 reproduce image information at 25Fps on a movie film 10 picked up at 24Fps to convert the information into a video signal of 625/50. A digital video tape recorder 12 records the video signal of 625/60 converted by the telecine device 11 onto a video tape cassette 13 with a scanning line number/field frequency which is not modified. A digital tape reproduction device 14 reproduces the video tape cassette 13 with the video signal recorded thereon at a field frequency of 50Hz. A modified digital video tape reproduction device 15 reproduces the video tape cassette 13 at a field frequency of 47.925Hz. An NTSC conversion section 16 converts a video signal of 625/47.952 into a video signal of 525/59.94.
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公开(公告)号：JP2586448B2
公开(公告)日：1997-02-26
申请号：JP3839986
申请日：1986-02-25
Applicant: SONY CORP
Inventor： OGAWA TETSUO
IPC: G11B27/36
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公开(公告)号：JPS62243496A
公开(公告)日：1987-10-23
申请号：JP8776786
申请日：1986-04-16
Applicant: SONY CORP
Inventor： TATEZAWA KAICHI , OGAWA TETSUO
Abstract: PURPOSE:To make the scale of hardware small without requiring any high- quality reproducing picture in designating an editing point by editing a digital VTR using 2 sets of reproducing devices and one set of recording device by means of one set of processor. CONSTITUTION:A processor 4 of an editing device of a digital VTR is provided with a recording processing circuit 5R and a reproduction processing circuit 5P processing a digital color signal of 4, 2, 2 system. The reproducing signal from 2 sets of reproducing devices l, 2 is fed to the circuit 5P of the processor 4 via video and audio switches 8, 9 respectively. The circuits 8, 9 halve the sampling frequency of the color video signal and make the total data quantity equal to that of the 4, 2, 2 system. The reproduced output of the circuit 5P of the processor 4 is separated by a reproducing switch circuit 11 and two reproduced pictures are monitored by monitors 14-16 to make the scale of hardware small.
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公开(公告)号：JPS62241192A
公开(公告)日：1987-10-21
申请号：JP8481286
申请日：1986-04-12
Applicant: SONY CORP
Inventor： NAGAI YASUO , OGAWA TETSUO
Abstract: PURPOSE:To facilitate the edition by recording a time code signal while the signal is retarded from an input digital video signal depending on the time required for the digital signal processing thereby making the correspondence between the time code signal and a picture complete. CONSTITUTION:A time code reproducing signal from other TVR or the like is fed to an input terminal 1 and a time code data by an input key or the like is fed to an input terminal 4 and fed to a delay circuit 5 via a changeover switch 3. The signal is retarded in the unit of frames at the circuit 5 in response to the time required for the digital signal processing and the result is fed to a time code signal generating circuit 6 and recorded by a recording/reproducing head 8. The analog video signal is inputted to an input terminal 11 and after the digital signal processing is applied by a recording signal processing circuit 13, the result is recorded by a video recording head 15. At the reproduction side, the total sum of the delay caused at each process is adjusted by a delay circuit, the relation of each output signal is made completely coincident thereby facilitating the edition.
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