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公开(公告)号：US20180026095A1
公开(公告)日：2018-01-25
申请号：US15714682
申请日：2017-09-25
Applicant: Texas Instruments Incorporated
Inventor： Raja Selvaraj , Anant Shankar Kamath , Byron Lovell Williams , Thomas D. Bonifield , John Kenneth Arch
IPC: H01L29/06 , H01L23/522 , H01L49/02 , H01L23/00
CPC classification number: H01L29/0646 , H01L21/265 , H01L21/761 , H01L23/5223 , H01L23/5227 , H01L23/5286 , H01L24/05 , H01L27/0676 , H01L28/10 , H01L28/20 , H01L28/40 , H01L28/60 , H01L2224/48463
Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
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公开(公告)号：US11841810B2
公开(公告)日：2023-12-12
申请号：US17244370
申请日：2021-04-29
Applicant: Texas Instruments Incorporated
Inventor： Suvadip Banerjee , Sreeram Subramanyam Nasum , Anant Shankar Kamath
IPC: G06F13/20 , G06F13/40 , H03K17/687 , G06F13/42
CPC classification number: G06F13/20 , G06F13/4086 , H03K17/6871 , G06F13/4282 , G06F2213/0016
Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.
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公开(公告)号：US20230028275A1
公开(公告)日：2023-01-26
申请号：US17382499
申请日：2021-07-22
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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公开(公告)号：US20230022405A1
公开(公告)日：2023-01-26
申请号：US17374319
申请日：2021-07-13
Applicant: Texas Instruments Incorporated
Inventor： Anant Shankar Kamath , Kanteti Amar , Bharath Kumar Singareddy , Rakesh Hariharan
IPC: H03K19/00
Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.
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公开(公告)号：US11482937B2
公开(公告)日：2022-10-25
申请号：US16804352
申请日：2020-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anant Shankar Kamath
Abstract: An isolation circuit for electrically isolating a first circuit operating at a first voltage from a second circuit operating at a second voltage that is different than the first voltage is provided. The isolation circuit includes: a first voltage source that operates at the first voltage, the first voltage source having a first supply rail and a second supply rail; an isolation device having a first input, a second input, a first output and a second output, the second input coupled to a first ground potential and the second output coupled to a second ground potential that is electrically isolated from the first ground potential by the isolation device; a first resistor coupled between the first supply rail and the first input of the isolation device; a second resistor coupled to the first input of the isolation device and the second input of the isolation device; and wherein the first output of the isolation device is coupled to the second circuit.
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Patent Agency Ranking
公开(公告)号：US11342835B2
公开(公告)日：2022-05-24
申请号：US16736235
申请日：2020-01-07
Applicant: Texas Instruments Incorporated
Inventor： Yihuang Lin , Abhijeeth Aarey Premanath , Anant Shankar Kamath
Abstract: A circuit for providing input surge protection in a digital input module, the circuit comprising a surge protection input stage, including a bridge rectifier coupled to receive the bidirectional input signal, and coupled to the unidirectional input of the digital input module. The bridge rectifier comprises TVS rectifiers TVS1 and TVS2, and diode rectifiers D2 and D3, intercoupled in a bridge rectifier configuration in which: TVS1 and TVS4 are transient voltage suppression diodes; and rectifiers D2 and D3 are rectifier diodes. Diodes TVS1 and TVS4 can be implemented as either respective unidirectional TVS diodes; or a single bidirectional TVS diode. The digital input module can be a digital input receiver, or a opto-isolator/coupler, or other digital input module.
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公开(公告)号：US10712426B2
公开(公告)日：2020-07-14
申请号：US16411285
申请日：2019-05-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kevin Paul Herring , Anant Shankar Kamath
Abstract: A digital input receiver system comprises a first input receiver having a first current limiter input, and a first voltage comparator input coupled to a first node. A first resistor is coupled between the first node and the first current limiter input. The first input receiver outputs a digital logic signal and is coupled to a second node. The receiver system further comprises a second input receiver having a second current limiter input, and a second voltage comparator input coupled to the second node. A second resistor is coupled between the second node and the second current limiter input. The second input receiver outputs a malfunction signal. The first and second input receivers are configured to limit current through the receiver system to less than an overcurrent threshold of the first and second input receivers.
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公开(公告)号：US20200079275A1
公开(公告)日：2020-03-12
申请号：US16526827
申请日：2019-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anant Shankar Kamath , Divyasree J.
Abstract: One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.
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公开(公告)号：US10281946B1
公开(公告)日：2019-05-07
申请号：US15996917
申请日：2018-06-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailendra Kumar Baranwal , Anant Shankar Kamath
IPC: G05F3/26 , H03K19/003 , H03K19/0185 , H03F3/16
Abstract: A bandgap voltage reference is provided in quasi-parallel with a resistor in the input path of a digital input circuit. Because of the quasi-parallel nature, the current used by the digital input circuit is limited to an amount based on the value of the external resistor. The input current is split between circuitry used to provide the logic signal across the selected isolation barrier and a sink transistor so that the current remains constant. This allows the digital input circuit to accurately limit input current without needing field-side power.
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公开(公告)号：US20180323746A1
公开(公告)日：2018-11-08
申请号：US16023277
申请日：2018-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anant Shankar Kamath , Sreeran N. S.
CPC classification number: H03D3/00 , H04L25/0268
Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.
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