公开(公告)号：US12166119B2

公开(公告)日：2024-12-10

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20240322006A1

公开(公告)日：2024-09-26

申请号：US18189870

申请日：2023-03-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/7786

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of a GaN semiconductor material. The GaN FET includes a contact etch stop and a stretch contact electrically connecting a source region with the contact etch stop. The contact etch stop may stretch over a p-type GaN gate structure towards a drain region to form a field plate connected to the source region. The contact etch stop provides a method to connect the field plate to the source region which allows efficient area scaling of space between the source region and the p-GaN gate structure. Disclosed examples provide an associated process flow for forming such GaN FETs.

公开(公告)号：US12027468B2

公开(公告)日：2024-07-02

申请号：US17176995

申请日：2021-02-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Young-Joon Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H05K1/02

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53228 ,  H01L29/7816 ,  H05K1/0216

Abstract: A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.

公开(公告)号：US20230197784A1

公开(公告)日：2023-06-22

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/0653

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20230061337A1

公开(公告)日：2023-03-02

申请号：US17463529

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  James Craig Ondrusek ,  Srikanth Krishnan

IPC: H01L29/417 ,  H01L23/482 ,  H01L27/098

Abstract: An integrated circuit, including a source region, a drain region, a channel region between the source region and the drain region, and a gate for inducing a conductive path through the channel region. The integrated circuit also includes structure, proximate a curved length of the gate, for inhibiting current flow along a portion of the channel region.

公开(公告)号：US20220130988A1

公开(公告)日：2022-04-28

申请号：US17081301

申请日：2020-10-27

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and/or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is/are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.

公开(公告)号：US10680093B2

公开(公告)日：2020-06-09

申请号：US15864157

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US10381456B2

公开(公告)日：2019-08-13

申请号：US15587021

申请日：2017-05-04

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/778 ,  H01L29/66 ,  H01L23/535 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.

公开(公告)号：US09882041B1

公开(公告)日：2018-01-30

申请号：US15353857

申请日：2016-11-17

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/3083 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/66462

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US09553151B2

公开(公告)日：2017-01-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L27/085

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。