公开(公告)号：US20230055211A1

公开(公告)日：2023-02-23

申请号：US17406150

申请日：2021-08-19

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US20220037280A1

公开(公告)日：2022-02-03

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20210328367A1

公开(公告)日：2021-10-21

申请号：US17232849

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q23/00 ,  H01L23/66 ,  H01Q1/22

Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including ≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.

公开(公告)号：US20210175326A1

公开(公告)日：2021-06-10

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

公开(公告)号：US10892405B2

公开(公告)日：2021-01-12

申请号：US16404978

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US12191259B2

公开(公告)日：2025-01-07

申请号：US17569724

申请日：2022-01-06

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495 ,  H01L25/00 ,  H01L25/18 ,  H03K17/042

Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

公开(公告)号：US20240178154A1

公开(公告)日：2024-05-30

申请号：US18070708

申请日：2022-11-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen ,  Jaimal Mallory Williamson

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a molded package structure, where the multilevel package substrate has opposite first and second substrate sides, first and second conductive pads spaced apart from one another along the first substrate side, and a conductive substrate terminal that is exposed along the second substrate side and is electrically coupled to the second conductive pad. The semiconductor die is attached to the first substrate side and has opposite first and second die sides, and a die terminal along the first die side, the die terminal electrically coupled to the first conductive pad. The molded has a package side, a metal shield along the package side, and a conductive package via that extends through the molded package structure and electrically couples the metal shield to the second conductive pad.

公开(公告)号：US11978699B2

公开(公告)日：2024-05-07

申请号：US17406150

申请日：2021-08-19

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L21/6835 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2224/81385 ,  H01L2224/81815

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US20240120297A1

公开(公告)日：2024-04-11

申请号：US17958254

申请日：2022-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jie Chen ,  Rajen Maricon Murugan ,  Chittranjan Mohan Gupta ,  Yiqi Tang

IPC: H01L23/66

CPC classification number: H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: An apparatus includes: a first conductor layer patterned into parallel strips having a first end and an opposite second end formed on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers extending through the dielectric material; a second conductor layer in the multilayer package substrate spaced from the first conductor layer, the second conductor layer patterned into parallel strips having a first end and a second end, the second conductor layer coupled to the first conductor layer by vertical connectors formed of the conductive vertical connection layers at the first end and the second end, and a semiconductor die mounted to the device side surface of the multilayer package substrate that is spaced from and coupled to the second conductor.

公开(公告)号：US20240112997A1

公开(公告)日：2024-04-04

申请号：US18482944

申请日：2023-10-09

Applicant: Texas Instruments Incorporated

Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/16227

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.