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公开(公告)号：US20230320229A1
公开(公告)日：2023-10-05
申请号：US18195383
申请日：2023-05-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号：US11778922B2
公开(公告)日：2023-10-03
申请号：US17533003
申请日：2021-11-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L41/47 , H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80 , H10N35/01
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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公开(公告)号：US20230200088A1
公开(公告)日：2023-06-22
申请号：US18113070
申请日：2023-02-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
CPC classification number: H10B61/00 , H01F41/34 , G11C11/161 , H01F10/3254 , H10N50/01 , H10N50/80
Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness
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公开(公告)号：US20220392850A1
公开(公告)日：2022-12-08
申请号：US17369936
申请日：2021-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Chin-Chia Yang , Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai
IPC: H01L23/00 , H01L23/522 , H01L29/417 , H01L21/02
Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.
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公开(公告)号：US20220238800A1
公开(公告)日：2022-07-28
申请号：US17180876
申请日：2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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Patent Agency Ranking
公开(公告)号：US20220238468A1
公开(公告)日：2022-07-28
申请号：US17159080
申请日：2021-01-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC: H01L23/00
Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.
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公开(公告)号：US20250112184A1
公开(公告)日：2025-04-03
申请号：US18979653
申请日：2024-12-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC: H01L23/00
Abstract: A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.
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公开(公告)号：US20250040158A1
公开(公告)日：2025-01-30
申请号：US18233899
申请日：2023-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai , Chung-Yi Chiu
IPC: H10K10/10
Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.
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公开(公告)号：US20250038103A1
公开(公告)日：2025-01-30
申请号：US18233877
申请日：2023-08-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai , Chung-Yi Chiu
IPC: H01L23/522 , H01L23/36 , H01L23/528
Abstract: A structure of an MIM capacitor and a heat sink include a dielectric layer. The dielectric layer includes a capacitor region and a heat dispensing region. A bottom electrode is embedded in the dielectric layer. A first heat conductive layer covers the dielectric layer. A capacitor dielectric layer is disposed on the first heat conductive layer within the capacitor region. A second heat conductive layer covers and contacts the capacitor dielectric layer and the first heat conductive layer. A top electrode is disposed within the capacitor region and the heat dispensing region and covers the second heat conductive layer. A first heat sink is disposed within the heat dispensing region and contacts the top electrode. A second heat sink is disposed within the heat dispensing region and contacts the first heat conductive layer and the second heat conductive layer.
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公开(公告)号：US12127413B2
公开(公告)日：2024-10-22
申请号：US18113070
申请日：2023-02-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
CPC classification number: H10B61/00 , G11C11/161 , H01F10/3254 , H01F41/34 , H10N50/01 , H10N50/80
Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness
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