公开(公告)号：US20210185358A1

公开(公告)日：2021-06-17

申请号：US17185683

申请日：2021-02-25

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC. ,  HUMAX CO., LTD.

Inventor： Jaehong Jung ,  Juhyung SON ,  Dongcheol KIM ,  Geonjung KO ,  Jinsam KWAK

IPC: H04N19/625 ,  H04N19/61 ,  H04N19/176 ,  H04N19/12

Abstract: Disclosed is a video signal processing method comprising the steps of: obtaining at least one transform block for a residual signal of a current block from a video signal bitstream; determining, on the basis of length information of a first side of the transform block, a horizontal transform kernel for horizontal transformation of the transform block, regardless of the length of a second side of the transform block, which is orthogonal to the first side; determining, on the basis of length information of the second side, a vertical transform kernel for vertical transformation of the transform block, regardless of the length of the first side; obtaining the residual signal of the current block by performing, on the transform block, inverse transformation using the horizontal transform kernel and the vertical transform kernel; and reconstructing the current block on the basis of the obtained residual signal.

公开(公告)号：US20210051319A1

公开(公告)日：2021-02-18

申请号：US17089267

申请日：2020-11-04

Applicant: Wilus Institute of Standards and Technology Inc. ,  Humax Co., Ltd.

Inventor： Dongcheol KIM ,  Geonjung KO ,  Jaehong JUNG ,  Juhyung SON ,  Jinsam KWAK

IPC: H04N19/105 ,  H04N19/176

Abstract: A video signal processing method comprises the steps of: acquiring reference samples on a first side of a current block and reference samples on a second side thereof on the basis of pre-restored samples neighboring the current block; acquiring a direct current (DC) value for a prediction of the current block on the basis of a reference sample set composed of at least some of the reference samples on the first side and the reference samples on the second side, wherein the reference sample set includes the number of reference samples raised to a power of 2, obtained by excluding some of the reference samples on the first side and the reference samples on the second side, if the length of the first side and the length of the second side are different; and restoring the current block on the basis of the DC value.

公开(公告)号：US20240406410A1

公开(公告)日：2024-12-05

申请号：US18689066

申请日：2022-09-05

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Dongcheol KIM ,  Kyungyong KIM ,  Juhyung SON ,  Jinsam KWAK

IPC: H04N19/157 ,  H04N19/117 ,  H04N19/132 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/70

Abstract: An apparatus for decoding a video signal comprises a processor, wherein the processor parses a first syntax element that is a general constraint information (GCI) syntax element, parses a second syntax element that indicates whether an LIC mode is available for a current sequence, and parses a third syntax element that indicates whether the LIC mode is used in a current block on the basis of a parsing result of the second syntax element.

公开(公告)号：US20240323446A1

公开(公告)日：2024-09-26

申请号：US18731091

申请日：2024-05-31

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Dongcheol KIM ,  Geonjung KO ,  Jaehong JUNG ,  Juhyung SON ,  Jinsam KWAK

IPC: H04N19/70 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/186

CPC classification number: H04N19/70 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/186

Abstract: A video signal decoding device comprises a processor which: decodes a general constraint information (GCI) syntax included in a bitstream of a video signal; and decodes the bitstream on the basis of the result of decoding the GCI syntax, wherein the GCI syntax includes a GCI syntax element for configuring the value of an SPS syntax element indicating whether it is possible to use a palette mode included in a sequence parameter set (SPS) raw byte sequence payload (RBSP) syntax.

公开(公告)号：US20240305830A1

公开(公告)日：2024-09-12

申请号：US18665009

申请日：2024-05-15

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Dongcheol KIM ,  Jaehong JUNG ,  Geonjung KO ,  Juhyung SON ,  Jinsam KWAK

IPC: H04N19/70 ,  H04N19/172 ,  H04N19/82

CPC classification number: H04N19/70 ,  H04N19/172 ,  H04N19/82

Abstract: A video signal decoding device comprises a processor, wherein: the processor decodes a sequence parameter set (SPS) raw byte sequence payload (RBSP) syntax included in a bitstream of a video signal, and decodes the bitstream on the basis of the decoding result of the SPS RBSP syntax; the SPS RBSP syntax includes a first syntax element related to the number of one or more sub-pictures configuring one picture, and a second syntax element indicating whether to process a boundary of the one or more sub-pictures as a boundary of the one picture on the basis of the first syntax element; and the second syntax element is parsed only when the number of the one or more sub-pictures is two or more.

公开(公告)号：US20240040156A1

公开(公告)日：2024-02-01

申请号：US18360645

申请日：2023-07-27

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Geonjung KO ,  Dongcheol KIM ,  Juhyung SON ,  Jaehong JUNG ,  Jinsam KWAK

IPC: H04N19/70 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/70 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: A video signal processing method may comprise the steps of: acquiring a first syntax element indicating whether a subblock-based merging mode is applied to a current block; acquiring a second syntax element indicating whether a merging mode using motion vector difference is applied to the current block, when the first syntax element indicates that the subblock-based merging mode is not applied to the current block; and acquiring a third syntax element indicating a candidate to be used in inter-prediction for the current block, among candidates contained in a mergence candidate list for the current block, when the second syntax element indicates that the merging mode using motion vector difference is applied to the current block.

公开(公告)号：US20230113874A1

公开(公告)日：2023-04-13

申请号：US18065839

申请日：2022-12-14

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Geonjung KO ,  Dongcheol KIM ,  Juhyung SON ,  Jaehong JUNG ,  Jinsam KWAK

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/70

Abstract: A video signal processing method comprises the steps of: receiving information for prediction of a current block; determining whether or not a merge mode is applied to the current block on the basis of the information for prediction; when a merge mode is applied to the current block, obtaining a first syntax element indicating whether or not a combined prediction is applied to the current block, wherein the combined prediction indicates a prediction mode that combines inter-prediction and intra-prediction; generating an inter-prediction block and an intra-prediction block of the current block when the first syntax element indicates that the combined prediction is applied to the current block; and generating a combined prediction block of the current block by weighted-summing the inter-prediction block and the intra-prediction block.

公开(公告)号：US20230110989A1

公开(公告)日：2023-04-13

申请号：US18065919

申请日：2022-12-14

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.

Inventor： Dongcheol KIM ,  Jaehong JUNG ,  Geonjung KO ,  Juhyung SON ,  Jinsam KWAK

IPC: H04N19/70 ,  H04N19/172 ,  H04N19/82

Abstract: A video signal decoding device comprises a processor, wherein: the processor decodes a sequence parameter set (SPS) raw byte sequence payload (RBSP) syntax included in a bitstream of a video signal, and decodes the bitstream on the basis of the decoding result of the SPS RBSP syntax; the SPS RBSP syntax includes a first syntax element related to the number of one or more sub-pictures configuring one picture, and a second syntax element indicating whether to process a boundary of the one or more sub-pictures as a boundary of the one picture on the basis of the first syntax element; and the second syntax element is parsed only when the number of the one or more sub-pictures is two or more.

公开(公告)号：US20220279162A1

公开(公告)日：2022-09-01

申请号：US17629385

申请日：2020-07-24

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC. ,  HUMAX CO., LTD.

Inventor： Geonjung KO ,  Dongcheol KIM ,  Juhyung SON ,  Jaehong JUNG ,  Jinsam KWAK

IPC: H04N19/105 ,  H04N19/186 ,  H04N19/33 ,  H04N19/176 ,  H04N19/167 ,  H04N19/132 ,  H04N19/159 ,  H04N19/593

Abstract: A method for processing a video signal, of the present disclosure, comprising the steps of: parsing, from a bitstream, upper level merge with MVD (MMVD) activation information (sps_mmvd_enabled_flag) indicating whether the upper level MMVD including a current block is usable; parsing, from the bitstream, MMVD merge information (mmvd_merge_flag) indicating whether the MMVD is used in the current block, if the upper level MMVD activation information indicates the activation of the MMVD; parsing MMVD distance-related information (mmvd_distance_idx) and MMVD direction-related information (mmvd_direction_idx), if the MMVD merge information indicates that the MMVD is used in the current block; and obtaining MMVD information (mMvdLX) based on the MMVD distance-related information and the MMVD direction-related information, wherein the MMVD information is greater than or equal to −2{circumflex over ( )}17 and is less than or equal to 2{circumflex over ( )}17−1.

公开(公告)号：US20220210474A1

公开(公告)日：2022-06-30

申请号：US17697811

申请日：2022-03-17

Applicant: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC. ,  HUMAX CO., LTD.

Inventor： Jaehong JUNG ,  Juhyung SON ,  Dongcheol KIM ,  Geonjung KO ,  Jinsam KWAK

IPC: H04N19/625 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

Abstract: A video signal processor is configured to: obtain at least one transform block for a residual signal of a current block from a video signal bitstream, wherein the transform block comprises a plurality of transform coefficients two-dimensionally arranged, determine, on the basis of length information of a first side of the transform block, a horizontal transform kernel for horizontal transformation of the transform block, regardless of a length of a second side of the transform block, which is orthogonal to the first side, determine, on the basis of length information of the second side, a vertical transform kernel for vertical transformation of the transform block, regardless of a length of the first side, obtain the residual signal of the current block by performing, on the transform block, inverse transformation using the horizontal transform kernel and the vertical transform kernel, and reconstruct the current block based on the residual signal.